SuccessChanges

Summary

  1. [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg (details)
  2. [AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize. (details)
  3. [docs] Sketch outline for HowToUpdateDebugInfo.rst (details)
  4. [os_log][test] Remove -O1 from a test, NFC (details)
Commit 19ff00dab875d6184618c756df01b57acb908e82 by Amara Emerson
[AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg
between the two instructions.

If there's a pattern like:
$xA = ADRP foo @PAGE
[some killing use of reg Xb]
$Xb = ADDXri $Xa, 0, @PAGEOFF

CollectLOH would create an AdrpAdd LOH that resulted in the linker optimizing
this sequence into:
$xB = ADR foo
[some killing use of reg $Xb]
... and therefore clobbers the live $Xb register that was used by the
instruction in between.

This was discovered by a GlobalISel patch D78465 which broke up global variable
accesses into two pseudos, which in some cases could be moved apart.

Differential Revision: https://reviews.llvm.org/D80834
The file was addedllvm/test/CodeGen/AArch64/loh-use-between-adrp-add.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64CollectLOH.cpp
Commit f573d489b6fccca85e0f2b3765aa17a364a4b0a8 by Amara Emerson
[AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize.

The concept of G_GLOBAL_VALUE is nice and simple, but always using it as the
representation for global var addressing until selection time creates some
problems in optimizing accesses in certain code/relocation models.

The problem comes from trying to optimize adrp -> add -> load/store sequences
in the most common "small" code model. These accesses can be optimized into an
adrp -> load with the add offset being folded into the load's immediate field.
If we try to keep all global var references as a single generic instruction
then by the time we get to the complex operand trying to match these, we end up
generating an adrp at the point of use. The real issue here is that we don't
have any form of CSE during selection, so the code size will bloat from many
redundant adrp's.

This patch custom legalizes small code mode non-GOT G_GLOBALs into target ADRP
and a new "target specific generic opcode" G_ADD_LOW. We also teach the
localizer to localize these instructions via the custom hook that was added
recently. Finally, the complex pattern for indexed loads/stores is extended to
try to fold these G_ADD_LOW instructions into the load immediate.

On -O0 CTMark, we see a 0.8% geomean code size improvement. We should also see
some minor performance improvements too.

Differential Revision: https://reviews.llvm.org/D78465
The file was addedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-global.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
The file was modifiedllvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/dllimport.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-custom-call-saved-reg.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64LegalizerInfo.h
Commit b429a0fef047867255e9cb65379677b2af7bb61b by Vedant Kumar
[docs] Sketch outline for HowToUpdateDebugInfo.rst

Summary:
Sketch the outline for a new document that explains how to update debug
info in various kinds of code transformations.

Some of the guidelines that belong in HowToUpdateDebugInfo.rst were in
SourceLevelDebugging.rst already under the debugify section. It seems
like the distinction between the two docs ought to be that the former is
more prescriptive, while the latter is more descriptive.

To that end I've consolidated the "how to update debug info" guidelines
which were in SourceLevelDebugging.rst into the new doc, along with the
information about using "debugify" to test transformations. Since we've
added a mir-debugify pass, I've described that as well.

Reviewers: aprantl, jmorse, chrisjackson, dsanders

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80052
The file was addedllvm/docs/HowToUpdateDebugInfo.rst
The file was modifiedllvm/docs/SourceLevelDebugging.rst
The file was modifiedllvm/docs/UserGuides.rst
Commit a66e1d2aa943959e158821be8956109cb5ef3b3b by Vedant Kumar
[os_log][test] Remove -O1 from a test, NFC
The file was modifiedclang/test/CodeGenObjCXX/os_log.mm