Changes

Summary

Fix 132e57bc597bd3f50174b7d286c43f76b47f11c1 (details)
[DAGCombiner] Fold fmin/fmax with INF / FLT_MAX (details)
[InstCombine] Simplify select operand based on equality condition (details)
[ms] [llvm-ml] Add missing built-in type aliases (details)
[ms] [llvm-ml] Fix struct padding logic (details)
[ms] [llvm-ml] Add support for size queries in MASM (details)
[ms] [llvm-ml] Add basic support for SEH, including PROC FRAME (details)
[ARM] Add more tests for vecreduce soft float legalization (NFC) (details)
[Legalize][ARM][X86] Add float legalization for VECREDUCE (details)
[libc] Extend MPFRMatcher to handle 2-input-1-output and support hypot function. (details)
[libc++] Use LLVM 11 instead of trunk on build bots (details)
[AArch64] Add additional vecreduce fmax/fmin legalization tests (NFC) (details)
[PowerPC] Implement Thread Local Storage Support for Local Exec (details)
[ELF] Add documentation for --warn-backrefs: a GNU ld compatibility checking tool (and lesser of layering detection) (details)
[FastISel] Bail out of selectGetElementPtr for vector GEPs. (details)

Commit a3bc0401d436d8c7d2dd5b54e13b81333d53bdff by walter erquinigo Fix 132e57bc597bd3f50174b7d286c43f76b47f11c1 Compile error found in http://lab.llvm.org:8011/builders/lldb-x86_64-debian/builds/17403/steps/build/logs/stdio Simple fix
	lldb/tools/lldb-vscode/lldb-vscode.cpp
Commit 8e69c3cde8eed94be226bdef1ff6cedda3a33bc4 by nikita.ppv [DAGCombiner] Fold fmin/fmax with INF / FLT_MAX Similar to D87415, this folds the various float min/max opcodes with a constant INF or -INF operand, or FLT_MAX / -FLT_MAX operand if the ninf flag is set. Some of the folds are only possible under nnan. The fminnum(X, INF) with nnan and fmaxnum(X, -INF) with nnan cases are needed to improve the VECREDUCE_FMIN/FMAX lowerings on X86, the rest is here for the sake of completeness. Differential Revision: https://reviews.llvm.org/D87571
	llvm/test/CodeGen/ARM/fminmax-folds.ll
	llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit cfff88c03cf9e9b72906a41fd11e06721d54f293 by nikita.ppv [InstCombine] Simplify select operand based on equality condition For selects of the type X == Y ? A : B, check if we can simplify A by using the X == Y equality and replace the operand if that's possible. We already try to do this in InstSimplify, but will only fold if the result of the simplification is the same as B, in which case the select can be dropped entirely. Here the select will be retained, just one operand simplified. As we are performing an actual replacement here, we don't have problems with refinement / poison values. Differential Revision: https://reviews.llvm.org/D87480
	llvm/test/Transforms/InstCombine/rem.ll
	llvm/test/Transforms/InstCombine/select.ll
	llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
	llvm/test/Transforms/InstCombine/select-binop-cmp.ll
Commit da17e0d5c1dfabcba887e323b1aabc8cc4342cd6 by epastor [ms] [llvm-ml] Add missing built-in type aliases Add signed aliases for integral types, as well as the "DF" abbreviation for the FWORD type. Reviewed By: thakis Differential Revision: https://reviews.llvm.org/D87246
	llvm/lib/MC/MCParser/MasmParser.cpp
	llvm/test/tools/llvm-ml/builtin_types.test
Commit 7c44ee8e1937c7402a106f3fa6a356caa73a14e8 by epastor [ms] [llvm-ml] Fix struct padding logic MASM structs are end-padded to have size a multiple of the smaller of the requested alignment and the size of their largest field (taken recursively, if they have a field of STRUCT type). This matches the behavior of ml.exe and ml64.exe. Our original implementation followed the MASM 6.0 documentation, which instead specified that MASM structs were padded to a multiple of their requested alignment. Reviewed By: thakis Differential Revision: https://reviews.llvm.org/D87248
	llvm/test/tools/llvm-ml/struct_alignment.test
	llvm/lib/MC/MCParser/MasmParser.cpp
Commit 20201dc76aaf68eb940eb14bfc6dd4983292fb79 by epastor [ms] [llvm-ml] Add support for size queries in MASM Add support for size inference, sizeof, typeof, and lengthof. Reviewed By: thakis Differential Revision: https://reviews.llvm.org/D86947
	llvm/test/tools/llvm-ml/size_inference.test
	llvm/include/llvm/MC/MCParser/MCAsmParser.h
	llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
	llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
	llvm/test/tools/llvm-ml/type_operators.test
	llvm/lib/MC/MCParser/AsmParser.cpp
	llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
	llvm/test/tools/llvm-ml/struct.test
	llvm/lib/MC/MCParser/MasmParser.cpp
Commit 23a2b03221c5664fefc658c3eb26e7b6ecd1a1e8 by epastor [ms] [llvm-ml] Add basic support for SEH, including PROC FRAME Add basic support for SEH, including PROC FRAME Reviewed By: thakis Differential Revision: https://reviews.llvm.org/D86948
	llvm/test/tools/llvm-ml/proc_frame.test
	llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
	llvm/test/tools/llvm-ml/proc.test
	llvm/lib/MC/MCParser/COFFMasmParser.cpp
	llvm/lib/MC/MCParser/MasmParser.cpp
Commit c0e3996bc7087a27e685c734480c0b92ff427d37 by nikita.ppv [ARM] Add more tests for vecreduce soft float legalization (NFC) This mirrors the existing fadd tests to fmul, fmin and fmax.
	llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll
	llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
	llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll
Commit 53f36f06afbc02d1ab96e3789b41ddeafe31f40e by nikita.ppv [Legalize][ARM][X86] Add float legalization for VECREDUCE This adds SoftenFloatRes, PromoteFloatRes and SoftPromoteHalfRes legalizations for VECREDUCE, to fill the remaining hole in the SDAG legalization. These legalizations simply expand the reduction and let it be recursively legalized. For the PromoteFloatRes case at least it is possible to do better than that, but it's pretty tricky (because we need to consider the interaction of three different vector legalizations and the type promotion) and probably not really worthwhile. I haven't added ExpandFloatRes support, as I am not familiar with ppc_fp128. Differential Revision: https://reviews.llvm.org/D87569
	llvm/lib/Target/ARM/ARMTargetTransformInfo.h
	llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
	llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
	llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll
	llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
	llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll
	llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
	llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
	llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
Commit abf1c82dcc5c54f2bbd65eb7b30cc40de2bd7147 by lntue [libc] Extend MPFRMatcher to handle 2-input-1-output and support hypot function. Differential Revision: https://reviews.llvm.org/D87514
	libc/utils/MPFRWrapper/MPFRUtils.h
	libc/utils/MPFRWrapper/MPFRUtils.cpp
Commit f06090243d870c2c0f6f1551eff0688a45fab298 by Louis Dionne [libc++] Use LLVM 11 instead of trunk on build bots Somehow the snapshot of LLVM trunk we use was seeing failures.
	libcxx/utils/docker/debian9/buildbot/docker-compose.yml
Commit cc947207283f934c72af0eb0b1a08978c59d40a2 by nikita.ppv [AArch64] Add additional vecreduce fmax/fmin legalization tests (NFC) Add a vector widening test with ninf flag to the existing fmax tests, and mirror them over into fmin tests.
	llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
	llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
Commit c0f199e5667a862819d333847059cfaa95354111 by albionapc [PowerPC] Implement Thread Local Storage Support for Local Exec This patch is the initial support for the Local Exec Thread Local Storage model to produce code sequence and relocations correct to the ABI for the model when using PC relative memory operations. Patch by: Kamau Bridgeman Differential Revision: https://reviews.llvm.org/D83404
	llvm/lib/Target/PowerPC/PPCInstrPrefix.td
	llvm/include/llvm/BinaryFormat/ELFRelocs/PowerPC64.def
	llvm/test/MC/PowerPC/pcrel-tls-local-exec-address-load-reloc.s
	llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll
	llvm/lib/Target/PowerPC/PPCISelLowering.cpp
	llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
	llvm/test/MC/PowerPC/pcrel-tls-local-exec-value-load-reloc.s
	llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
	llvm/lib/Target/PowerPC/PPCISelLowering.h
	llvm/lib/Target/PowerPC/PPCInstrInfo.td
	llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Commit f6f34024e9a4870eea6733dcbab6de89cc435262 by i [ELF] Add documentation for --warn-backrefs: a GNU ld compatibility checking tool (and lesser of layering detection) Differential Revision: https://reviews.llvm.org/D86762
	lld/docs/ELF/warn_backrefs.rst
	lld/docs/index.rst
Commit 4208ea3e19f8e3e8cd35e6f5a6c43f4aa066c6ec by craig.topper [FastISel] Bail out of selectGetElementPtr for vector GEPs. The code that decomposes the GEP into ADD/MUL doesn't work properly for vector GEPs. It can create bad COPY instructions or possibly assert. For now just bail out to SelectionDAG. Fixes PR45906
	llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
	llvm/test/CodeGen/X86/masked_gather_scatter.ll