SuccessChanges

Summary

  1. Bump Android NDK version to r21. (details)
  2. Revert "Bump Android NDK version to r21." (details)
Commit 9822b13842a6f476f023ef282d329c276d165a7c by eugenis
Bump Android NDK version to r21.
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_android.sh (diff)
Commit b4f7979eb1e77f6f65fa08d9a557913af41550d7 by eugenis
Revert "Bump Android NDK version to r21."
This reverts commit 9822b13842a6f476f023ef282d329c276d165a7c.
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_android.sh (diff)

Summary

  1. Add test for spaceship operator to __config (details)
  2. [DA] Don't propagate from unreachable blocks (details)
  3. Support Swift calling convention for WebAssembly targets (details)
  4. Resubmit: [DA][TTI][AMDGPU] Add option to select GPUDA with TTI (details)
  5. Allow combining of extract_subvector to extract element (details)
  6. [AMDGPU] Allow narrowing muti-dword loads (details)
  7. [PGO] Attach appropriate funclet operand bundles to value profiling (details)
  8. [AMDGPU] Bundle loads before post-RA scheduler (details)
  9. Make address-space-lambda.cl pass on 32-bit Windows (details)
  10. [gn build] Port 555d8f4ef5e (details)
  11. Include <cstdlib> for std::abort() in clangd (details)
  12. [GlobalsAA] Add back a check to intrinsic_addresstaken.ll to see if the (details)
  13. AMDGPU/GlobalISel: Add selection tests for G_ATOMICRMW_ADD (details)
  14. AMDGPU: Don't check constant address space for atomic stores (details)
  15. TableGen: Work around assert on Mips register definitions (details)
  16. TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG (details)
  17. Correct NumLoads in clustering (details)
Commit 5dda92fcb0ce9206f831aa7cddf24421dcf044d7 by dave
Add test for spaceship operator to __config
Summary: The libcxx test suite auto-detects spaceship operator, but
__config does not. This means that the libcxx test suite has been broken
for over a month when using top-of-tree clang. This also really ought to
be fixed before 10.0.
See: bc633a42dd409dbeb456263e3388b8caa4680aa0
Reviewers: chandlerc, mclow.lists, EricWF, ldionne, CaseyCarter
Reviewed By: EricWF
Subscribers: broadwaylamb, hans, dexonsmith, tstellar, llvm-commits,
libcxx-commits
Tags: #libc, #llvm
Differential Revision: https://reviews.llvm.org/D72980
The file was modifiedlibcxx/include/__config
Commit 37aa16ebb713c1d76d93f7d29419fd6ea88ac72c by Austin.Kerbow
[DA] Don't propagate from unreachable blocks
Summary: Fixes crash that could occur when a divergent terminator has an
unreachable parent.
Reviewers: rampitec, nhaehnle, arsenm
Subscribers: jvesely, wdng, hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73323
The file was modifiedllvm/lib/Analysis/DivergenceAnalysis.cpp
The file was addedllvm/test/Analysis/DivergenceAnalysis/AMDGPU/unreachable-loop-block.ll
Commit c5bd3d07262ffda5b21576b9e1e2d2dd2e51fb4b by dschuff
Support Swift calling convention for WebAssembly targets
This adds basic support for the Swift calling convention with
WebAssembly targets.
Reviewed By: dschuff
Differential Revision: https://reviews.llvm.org/D71823
The file was modifiedclang/lib/Basic/Targets/WebAssembly.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
Commit c2266463377a1727f0627fe4db9a88a1b33a9f4d by Austin.Kerbow
Resubmit: [DA][TTI][AMDGPU] Add option to select GPUDA with TTI
Summary: Enable the new diveregence analysis by default for AMDGPU.
Resubmit with test updates since GPUDA was causing failures on Windows.
Reviewers: rampitec, nhaehnle, arsenm, thakis
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye,
hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73315
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/workitem-intrinsics.ll
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/llvm.amdgcn.buffer.atomic.ll
The file was modifiedllvm/lib/Analysis/LegacyDivergenceAnalysis.cpp
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/no-return-blocks.ll
The file was modifiedllvm/include/llvm/Analysis/LegacyDivergenceAnalysis.h
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/loads.ll
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/phi-undef.ll
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/llvm.amdgcn.image.atomic.ll
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/intrinsics.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/atomics.ll
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/unreachable-loop-block.ll
Commit 7a94d4f4ee435386ff47f7f3ecad4e56608578b6 by Stanislav.Mekhanoshin
Allow combining of extract_subvector to extract element
Differential Revision: https://reviews.llvm.org/D73132
The file was modifiedllvm/test/CodeGen/ARM/vdup.ll
The file was modifiedllvm/test/CodeGen/ARM/vpadd.ll
The file was modifiedllvm/test/CodeGen/ARM/vext.ll
The file was modifiedllvm/test/CodeGen/X86/sse41.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
The file was modifiedllvm/test/CodeGen/ARM/vuzp.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 44b865fa7fea8243126c489df6604ae7ecee072a by Stanislav.Mekhanoshin
[AMDGPU] Allow narrowing muti-dword loads
Currently BE allows only a little load narrowing because of the fear it
will produce sub-dword ext loads. However, we can always allow narrowing
if we are shrinking one multi-dword load to another multi-dword load.
In particular we were unable to reduce s_load_dwordx8 into
s_load_dwordx4 if identity shuffle was used to extract low 4 dwords.
Differential Revision: https://reviews.llvm.org/D73133
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
Commit b35b7da4608426e099fc048319ebf50c11c984ea by andrew.kaylor
[PGO] Attach appropriate funclet operand bundles to value profiling
instrumentation calls
Patch by Chris Chrulski
When generating value profiling instrumentation, ensure the call gets
the correct funclet token, otherwise WinEHPrepare will turn the call
(and all subsequent instructions) into unreachable.
Differential Revision: https://reviews.llvm.org/D73221
The file was modifiedllvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
The file was addedllvm/test/Transforms/PGOProfile/indirect_call_profile_funclet.ll
The file was addedllvm/test/Transforms/PGOProfile/memop_profile_funclet.ll
Commit 555d8f4ef5ebb2cdce2636af5102ff944da5fef8 by Stanislav.Mekhanoshin
[AMDGPU] Bundle loads before post-RA scheduler
We are relying on atrificial DAG edges inserted by the
MemOpClusterMutation to keep loads and stores together in the post-RA
scheduler. This does not work all the time since it allows to schedule a
completely independent instruction in the middle of the cluster.
Removed the DAG mutation and added pass to bundle already clustered
instructions. These bundles are unpacked before the memory legalizer
because it does not work with bundles but also because it allows to
insert waitcounts in the middle of a store cluster.
Removing artificial edges also allows a more relaxed scheduling.
Differential Revision: https://reviews.llvm.org/D72737
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_write2st64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory_clause.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/salu-to-valu.ll
The file was addedllvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/select.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-lo16.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/idot8s.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/scratch-simple.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/half.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
The file was addedllvm/lib/Target/AMDGPU/SIPostRABundler.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/v_mac_f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot4u.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot8u.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sign_extend.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/v_madak_f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/idot4s.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/saddo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-store-crash.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/max.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-argument-types.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.v2i16.ll
Commit 698d1cd3b8154b3b74423386d3e111e6b756e87a by hans
Make address-space-lambda.cl pass on 32-bit Windows
Member functions will have the thiscall attribute on them.
The file was modifiedclang/test/SemaOpenCLCXX/address-space-lambda.cl
Commit 6530136fe3f90b3716f8a1f4b0b951b5fb604aaf by llvmgnsyncbot
[gn build] Port 555d8f4ef5e
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Commit 58592f6c49249293f79698cfcb31dba532e12603 by dimitry
Include <cstdlib> for std::abort() in clangd
This fixes a "not a member of 'std'" error with e.g. Fedora 32.
Closes: #105
The file was modifiedclang-tools-extra/clangd/Shutdown.cpp
Commit a107f864176300629afeb9f22be19513917b36bd by craig.topper
[GlobalsAA] Add back a check to intrinsic_addresstaken.ll to see if the
AVX and AVX512 bots still fail for it.
These bots failed for this several months ago and as a result, this
check was removed. If they still fail I'm going to try to see if I can
figure out why.
The file was modifiedllvm/test/Analysis/GlobalsModRef/intrinsic_addresstaken.ll
Commit 4fdae24733d223b773f2bd48081e5e147739afa5 by Matthew.Arsenault
AMDGPU/GlobalISel: Add selection tests for G_ATOMICRMW_ADD
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
Commit 84e035d8f1d635d202692e3c38c9c96aa1e08088 by Matthew.Arsenault
AMDGPU: Don't check constant address space for atomic stores
We define a separate list for storable address spaces. This saves entry
in the matcher table address space list.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
Commit d8328c0b6240234c8036f16c081ab7e8dc98cce8 by Matthew.Arsenault
TableGen: Work around assert on Mips register definitions
This would hit the "Biggest class wasn't first" assert in
getMatchingSubClassWithSubRegs in a future patch for EXTRACT_SUBREG
handling.
Mips defines 4 identical register classes (MSA128B, MSA128H, MSA128BW,
MSA128D). These have the same set of registers, and only differ by the
isel type. I believe this is an ill formed way of defining registers,
that probably is just to work around the inconvenience of mixing
different types in a single register class in DAG patterns.
Since these all have the same size, they would all sort to the
beginning, but you would not necessarily get the same super register at
the front as the assert enforces. Breaking the ambiguity by also sorting
by name doesn't work, since each of these register classes all want to
be first. Force sorting of the original register class if the size is
the same.
The file was modifiedllvm/utils/TableGen/CodeGenRegisters.cpp
Commit 9c346464c15c9f42fd641c33ca4c35b31556a661 by Matthew.Arsenault
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG
This previously only handled EXTRACT_SUBREGs from leafs, such as
operands directly in the original output. Handle extracting from a
result instruction.
The file was modifiedllvm/test/TableGen/GlobalISelEmitterSubreg.td
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-copy.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/select-ext.mir
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/shl-scalar-widening.ll
Commit be8e38cbd9785d4f4023b88150d14bd815265eef by Stanislav.Mekhanoshin
Correct NumLoads in clustering
Scheduler sends NumLoads argument into shouldClusterMemOps() one less
the actual cluster length. So for 2 instructions it will pass just 1.
Correct this number.
This is NFC for in tree targets.
Differential Revision: https://reviews.llvm.org/D73292
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Summary

  1. Rename test-suite test case to prevent NOEXE failures (details)
Commit b7ba2103c1cfdb7e717a8d02a58b1452aef0b636 by lei
Rename test-suite test case to prevent NOEXE failures
In the test-suite, we have two files:
SingleSource/UnitTests/Vector/Altivec/ld.reference_output
SingleSource/UnitTests/Vector/Altivec/ld.c
That need to have their name changed to:
SingleSource/UnitTests/Vector/Altivec/vec_ld.reference_output
SingleSource/UnitTests/Vector/Altivec/vec_ld.c
Because they cause other test cases in the directory to not produce
executable once the ld test is built. The reason for the failure is that
the ./ld is used as the linker when building other tests.
The file was removedSingleSource/UnitTests/Vector/Altivec/ld.reference_output
The file was addedSingleSource/UnitTests/Vector/Altivec/vec_ld.c
The file was removedSingleSource/UnitTests/Vector/Altivec/ld.c
The file was addedSingleSource/UnitTests/Vector/Altivec/vec_ld.reference_output