Changes

Summary

[clangd] Fix member/type name conflict caught by buildbots. (details)
[clangd] Fix fuzzer build after 7ba0779fbb41b6fa8 (details)
[clangd][remote] Make sure relative paths are absolute with respect to posix style (details)
[AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer (details)
[SplitKit] Cope with no live subranges in defFromParent (details)
[SystemZ] Support bare nop instructions (details)
[MLIR][SPIRV] Support different function control in (de)serialization (details)
[X86] Support Intel Key Locker (details)
[gn build] Port 413577a8790 (details)
[InstCombine] recognizeBSwapOrBitReverseIdiom - assert for correct bit providence indices. NFCI. (details)
[InstCombine] recognizeBSwapOrBitReverseIdiom - recognise zext(bswap(trunc(x))) patterns (PR39793) (details)
[mlir] Added support for rank reducing subviews (details)
[NFC][ARM] Add more LowOverheadLoop tests. (details)
[mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments (details)
[SCEV] Verify that all mapped SCEV AddRecs refer to valid loops. (details)

Commit 6342b38c5fee74df94d7b0c34e5a93b9b22763df by sam.mccall [clangd] Fix member/type name conflict caught by buildbots.
	clang-tools-extra/clangd/tool/ClangdMain.cpp
	clang-tools-extra/clangd/ClangdLSPServer.cpp
	clang-tools-extra/clangd/ClangdLSPServer.h
Commit d99f46c6eb8debaa1a14c122956177dc2a40ef9b by sam.mccall [clangd] Fix fuzzer build after 7ba0779fbb41b6fa8
	clang-tools-extra/clangd/fuzzer/clangd-fuzzer.cpp
Commit 64e8fd540ecc38ee3daf942499091589785e2733 by kadircet [clangd][remote] Make sure relative paths are absolute with respect to posix style Relative paths received from the server are always in posix style. So we need to ensure they are relative using that style, and not the native one. Differential Revision: https://reviews.llvm.org/D88507
	clang-tools-extra/clangd/index/remote/marshalling/Marshalling.cpp
Commit 0249df33fec16b728e2d33cae02f5da4c9f74e38 by Mirko.Brkusanin [AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer Check if operand of mul is constant value of one for certain atomic instructions in order to avoid making unnecessary instructions when -amdgpu-atomic-optimizer is present. Differential Revision: https://reviews.llvm.org/D88315
	llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
	llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
Commit cdac4492b4a523a888a013d42ea0a968f684ed59 by jay.foad [SplitKit] Cope with no live subranges in defFromParent Following on from D87757 "[SplitKit] Only copy live lanes", it is possible to split a live range at a point when none of its subranges are live. This patch handles that case by inserting an implicit def of the superreg. Patch by Quentin Colombet! Differential Revision: https://reviews.llvm.org/D88397
	llvm/lib/CodeGen/SplitKit.cpp
	llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
Commit 9f5da55f5d9299a76a4dfb67ef0324dbc1900826 by paulsson [SystemZ] Support bare nop instructions Add support of "nop" and "nopr" (without operands) to assembler. Review: Ulrich Weigand
	llvm/test/MC/SystemZ/insn-good.s
	llvm/lib/Target/SystemZ/SystemZInstrInfo.td
Commit 8c05c7c8d87c7ab02fca2a789dfcca4976c6601b by georgemitenk0v [MLIR][SPIRV] Support different function control in (de)serialization Added support for different function control in serialization and deserialization. Reviewed By: mravishankar Differential Revision: https://reviews.llvm.org/D88280
	mlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp
	mlir/test/Dialect/SPIRV/Serialization/module.mlir
	mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp
Commit 413577a8790407d75ba834fa5668c2632fe1851e by xiang1.zhang [X86] Support Intel Key Locker Key Locker provides a mechanism to encrypt and decrypt data with an AES key without having access to the raw key value by converting AES keys into “handles”. These handles can be used to perform the same encryption and decryption operations as the original AES keys, but they only work on the current system and only until they are revoked. If software revokes Key Locker handles (e.g., on a reboot), then any previous handles can no longer be used. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D88398
	llvm/lib/Support/X86TargetParser.cpp
	llvm/test/MC/X86/KEYLOCKER/keylocker-att.s
	clang/lib/CodeGen/CGBuiltin.cpp
	llvm/utils/TableGen/IntrinsicEmitter.cpp
	clang/include/clang/Basic/BuiltinsX86.def
	clang/include/clang/Driver/Options.td
	clang/lib/Headers/CMakeLists.txt
	clang/test/CodeGen/attr-target-x86.c
	llvm/test/MC/X86/KEYLOCKER/x86-64-keylocker-intel.s
	clang/lib/Headers/keylocker_wide_intrin.h
	clang/lib/Headers/immintrin.h
	llvm/lib/Target/X86/X86Subtarget.h
	llvm/include/llvm/IR/IntrinsicsX86.td
	clang/test/Preprocessor/x86_target_features.c
	llvm/test/MC/X86/KEYLOCKER/keylocker-intel.s
	clang/test/Driver/x86-target-features.c
	llvm/lib/Support/Host.cpp
	llvm/lib/Target/X86/X86.td
	llvm/lib/Target/X86/X86InstrInfo.td
	llvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-64-intel.txt
	llvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-32-intel.txt
	llvm/lib/IR/Function.cpp
	llvm/test/MC/X86/KEYLOCKER/x86-64-keylocker-att.s
	clang/test/CodeGen/X86/keylocker.c
	clang/lib/Basic/Targets/X86.h
	llvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-64-att.txt
	clang/lib/Basic/Targets/X86.cpp
	llvm/test/CodeGen/X86/keylocker-intrinsics.ll
	llvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-32-att.txt
	llvm/include/llvm/Support/X86TargetParser.def
	clang/lib/Headers/keylockerintrin.h
	llvm/lib/Target/X86/X86InstrKL.td
	llvm/lib/Target/X86/X86InstrInfo.td.rej
	llvm/lib/Target/X86/X86ISelLowering.cpp
Commit e39d7884a1f5c5c7136ba2e493e9ac313ccc78ed by llvmgnsyncbot [gn build] Port 413577a8790
	llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Commit ec3f24d4538d1c262377331c7b35ea66e023cf98 by llvm-dev [InstCombine] recognizeBSwapOrBitReverseIdiom - assert for correct bit providence indices. NFCI. As suggested by @spatel on D88316
	llvm/lib/Transforms/Utils/Local.cpp
Commit af47d40b9c68744eb66aa2ef779065e946aaa099 by llvm-dev [InstCombine] recognizeBSwapOrBitReverseIdiom - recognise zext(bswap(trunc(x))) patterns (PR39793) PR39793 demonstrated an issue where we fail to recognize 'partial' bswap patterns of the lower bytes of an integer source. In fact, most of this is already in place collectBitParts suitably tags zero bits, so we just need to correctly handle this case by finding the zero'd upper bits and reducing the bswap pattern just to the active demanded bits. Differential Revision: https://reviews.llvm.org/D88316
	llvm/lib/Transforms/Utils/Local.cpp
	llvm/test/Transforms/InstCombine/bswap.ll
Commit 14088a6f5d1ae597960833a366beb9acee8d65cb by limo [mlir] Added support for rank reducing subviews This commit adds support for subviews which enable to reduce resulting rank by dropping static dimensions of size 1. Differential Revision: https://reviews.llvm.org/D88534
	mlir/test/IR/invalid-ops.mlir
	mlir/test/IR/core-ops.mlir
	mlir/lib/Dialect/StandardOps/IR/Ops.cpp
	mlir/lib/Dialect/Vector/VectorTransforms.cpp
	mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit 3cbd01ddb9372b725dcea3dd5fed21ef5b3d9578 by sam.parker [NFC][ARM] Add more LowOverheadLoop tests.
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
Commit 0b17d4754a94b7129c2483762acd586783802b12 by limo [mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments Current setup for conv op vectorization does not enable user to specify tile sizes as well as dimensions for vectorization. In this commit we change that by adding tile sizes as pass arguments. Every dimension with corresponding tile size > 1 is automatically vectorized. Differential Revision: https://reviews.llvm.org/D88533
	mlir/test/lib/Transforms/TestConvVectorization.cpp
	mlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-ncw-call.mlir
	mlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-nwc-call.mlir
	mlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ndhwc-call.mlir
	mlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-call.mlir
	mlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-call.mlir
	mlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-call.mlir
	mlir/test/Conversion/LinalgToVector/linalg-to-vector.mlir
	mlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nhwc-call.mlir
	mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
	mlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nchw-call.mlir
	mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
	mlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ncdhw-call.mlir
Commit 0eab9d5823815c6520697f8d725c402c88e5d050 by flo [SCEV] Verify that all mapped SCEV AddRecs refer to valid loops. This check helps to guard against cases where expressions referring to invalidated/deleted loops are not properly invalidated. The additional check is motivated by the reproducer shared for 8fdac7cb7abb and I think in general make sense as a sanity check. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D88166
	llvm/lib/Analysis/ScalarEvolution.cpp