SuccessChanges

Summary

  1. [NFC] Fix file header filename to be Range.h (details)
  2. [NFC] Sort source files in Utility/CMakeLists.txt (details)
  3. Add -Wpoison-system-directories warning (details)
  4. [SDAG] Update generic code to conservatively check for isAtomic in (details)
  5. [libclang] Expose abort()-ing LLVM fatal error handler (details)
  6. [AArch64][GlobalISel] Support tail calling with swiftself parameters (details)
  7. Rename nonvolatile_load/store to simple_load/store [NFC] (details)
  8. [Test] Restructure check lines to show differences between modes more (details)
  9. AMDGPU: Inline constant when materalizing FI with add on gfx9 (details)
  10. LiveIntervals: Remove assertion (details)
  11. AMDGPU: Add immarg to llvm.amdgcn.init.exec.from.input (details)
  12. [libclang] Fix UninstallAbortingLLVMFatalErrorHandler test (details)
  13. The setUp/tearDown methods I added mssed up the test function; reorder. (details)
  14. [Target] Move InferiorCall to Process (details)
  15. DAG/GlobalISel: Correct type profile of bitcount ops (details)
  16. AMDGPU/GlobalISel: Select G_CTPOP (details)
  17. Revert r371785. (details)
  18. AMDGPU/GlobalISel: Legalize G_FMAD (details)
Commit d44d9e8cda0c4230ab7e52e06e7773aa8f8b9206 by clayborg
[NFC] Fix file header filename to be Range.h
llvm-svn: 371783
The file was modifiedllvm/include/llvm/DebugInfo/GSYM/Range.h
Commit decff073ee413dbc39a13b45592897b77e87552f by Jonas Devlieghere
[NFC] Sort source files in Utility/CMakeLists.txt
llvm-svn: 371784
The file was modifiedlldb/source/Utility/CMakeLists.txt
Commit 4fe2732161905a9bd53e09336851482a96b04ce9 by manojgupta
Add -Wpoison-system-directories warning
When using clang as a cross-compiler, we should not use system headers
to do the compilation. This CL adds support of a new warning flag
-Wpoison-system-directories which emits warnings if --sysroot is set and
headers from common host system location are used. By default the
warning is disabled.
The intention of the warning is to catch bad includes which are usually
generated by third party build system not targeting cross-compilation.
Such cases happen in Chrome OS when someone imports a new package or
upgrade one to a newer version from upstream.
Patch by: denik (Denis Nikitin)
llvm-svn: 371785
The file was modifiedclang/include/clang/Basic/DiagnosticCommonKinds.td
The file was addedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/lib/.keep
The file was addedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/include/c++/.keep
The file was modifiedclang/lib/Frontend/InitHeaderSearch.cpp
The file was addedclang/test/Frontend/warning-poison-system-directories.c
The file was addedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/include/.keep
The file was addedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/lib/gcc/.keep
The file was addedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/lib/.keep
Commit 079e2104633489e9b99c17c0c1426db11d69bb2f by listmail
[SDAG] Update generic code to conservatively check for isAtomic in
addition to isVolatile
This is the first sweep of generic code to add isAtomic bailouts where
appropriate. The intention here is to have the switch from AtomicSDNode
to LoadSDNode/StoreSDNode be close to NFC; that is, I'm not looking to
allow additional optimizations at this time. That will come later.  See
D66309 for context.
Differential Revision: https://reviews.llvm.org/D66318
llvm-svn: 371786
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
Commit f7d2376b98728a10143bd3bb715f07b01ee2f5d1 by Jan Korous
[libclang] Expose abort()-ing LLVM fatal error handler
Differential Revision: https://reviews.llvm.org/D66775
llvm-svn: 371787
The file was modifiedclang/tools/libclang/libclang.exports
The file was addedclang/include/clang-c/FatalErrorHandler.h
The file was modifiedclang/tools/libclang/CMakeLists.txt
The file was addedclang/unittests/libclang/CrashTests/LibclangCrashTest.cpp
The file was modifiedclang/tools/libclang/CIndex.cpp
The file was addedclang/tools/libclang/FatalErrorHandler.cpp
The file was modifiedclang/unittests/libclang/CMakeLists.txt
The file was addedclang/unittests/libclang/CrashTests/CMakeLists.txt
Commit 0c283cb50418e56fc3ad92d552480273751534d5 by Jessica Paquette
[AArch64][GlobalISel] Support tail calling with swiftself parameters
Swiftself uses a callee-saved register. We can tail call when the
register used in the caller and callee is the same.
This behaviour is equivalent to that in
`TargetLowering::parametersInCSRMatch`.
Update call-translator-tail-call.ll to verify that we can do this. When
we support inline assembly, we can write a check similar to the one in
the general swiftself.ll. For now, we need to verify that we get the
correct COPY instruction after call lowering.
Differential Revision: https://reviews.llvm.org/D67511
llvm-svn: 371788
The file was modifiedllvm/lib/Target/AArch64/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
Commit 0b4d67ca35b20e677a62b5ab64d7e64271ae7c65 by listmail
Rename nonvolatile_load/store to simple_load/store [NFC]
Implement the TODO from D66318.
llvm-svn: 371789
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.td
The file was modifiedllvm/lib/Target/X86/X86InstrCompiler.td
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFP.td
Commit 4a8916cf1a45a9ee5a95cc011f60ce10a02ff196 by listmail
[Test] Restructure check lines to show differences between modes more
clearly
With the landing of the previous patch (in particular D66318) there are
a lot fewer diffs now.  I added an experimental O0 line, and updated all
the tests to group experimental and non-experimental O0/O3 together.
Skimming the remaining diffs, there's only a few which are obviously
incorrect.  There's a large number which are questionable, so more todo.
llvm-svn: 371790
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
Commit 8382ce5f1b099e4cf8b1e15fe9efb6963740b6cc by Matthew.Arsenault
AMDGPU: Inline constant when materalizing FI with add on gfx9
This was relying on the SGPR usable for the carry out clobber to also be
used for the input. There was no carry out on gfx9. With no carry out
clobber to worry about, so the literal can just be directly used with a
VOP2 add.
llvm-svn: 371791
The file was addedllvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit b85c8c4bbdedc370968865ec017eeb87cb2bc69d by Matthew.Arsenault
LiveIntervals: Remove assertion
This testcase is invalid, and caught by the verifier. For the verifier
to catch it, the live interval computation needs to complete. Remove the
assert so the verifier catches this, which is less confusing.
In this testcase there is an undefined use of a subregister, and lanes
which aren't used or defined. An equivalent testcase with the
super-register shrunk to have no untouched lanes already hit this
verifier error.
llvm-svn: 371792
The file was modifiedllvm/lib/CodeGen/LiveInterval.cpp
The file was addedllvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
Commit 91b758f358096965abc2ceb53df683083cff0edd by Matthew.Arsenault
AMDGPU: Add immarg to llvm.amdgcn.init.exec.from.input
As far as I can tell this has to be a constant.
llvm-svn: 371793
The file was modifiedllvm/include/llvm/IR/IntrinsicsAMDGPU.td
Commit 5e4a03f03775422863e241326583ea74a94d0316 by Jan Korous
[libclang] Fix UninstallAbortingLLVMFatalErrorHandler test
llvm-svn: 371794
The file was modifiedclang/unittests/libclang/CrashTests/LibclangCrashTest.cpp
Commit 0a39ef4704a5934d6cecbd3afdc771732bed107d by Jason Molenda
The setUp/tearDown methods I added mssed up the test function; reorder.
Thanks to Ted Woodward for catching this one.
llvm-svn: 371795
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestWriteMemory.py
Commit 5b2b38e053b4638c08da4104e8bb5bd643fde737 by apl
[Target] Move InferiorCall to Process
Summary: InferiorCall is only ever used in Process, and it is not
specific to POSIX. By moving it to Process, we can remove all
dependencies on plugins from Process. Moving InferiorCall to Process
seems to achieve this quite well. Additionally, the name InferiorCall is
a little vague now, so we rename it something a bit more specific.
Reviewers: JDevlieghere, clayborg, compnerd, labath
Subscribers: lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D67472
llvm-svn: 371796
The file was modifiedlldb/source/Plugins/Process/Utility/InferiorCallPOSIX.h
The file was modifiedlldb/source/Plugins/Process/Utility/InferiorCallPOSIX.cpp
The file was modifiedlldb/source/Target/Process.cpp
The file was modifiedlldb/include/lldb/Target/Process.h
Commit b366329a34a1f2dc277f030df239236d43792fba by Matthew.Arsenault
DAG/GlobalISel: Correct type profile of bitcount ops
The result integer does not need to be the same width as the input.
AMDGPU, NVPTX, and Hexagon all have patterns working around the types
matching. GlobalISel defines these as being different type indexes.
llvm-svn: 371797
The file was modifiedllvm/lib/Target/Hexagon/HexagonPatterns.td
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/Sparc/SparcInstrInfo.td
The file was modifiedllvm/lib/Target/Sparc/SparcInstr64Bit.td
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/NVPTX/NVPTXInstrInfo.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.td
Commit 4a73c6eadae0c92771106f85fc77c32f60a1b30e by Matthew.Arsenault
AMDGPU/GlobalISel: Select G_CTPOP
llvm-svn: 371798
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit 38f6b3fd8dd7dc3a3b4eae63738d5d3a741b2227 by manojgupta
Revert r371785.
r371785 is causing fails on clang-hexagon-elf buildbots.
llvm-svn: 371799
The file was modifiedclang/include/clang/Basic/DiagnosticCommonKinds.td
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/lib/gcc/.keep
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/include/.keep
The file was modifiedclang/lib/Frontend/InitHeaderSearch.cpp
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/include/c++/.keep
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/lib/.keep
The file was removedclang/test/Frontend/warning-poison-system-directories.c
The file was removedclang/test/Frontend/Inputs/sysroot_x86_64_cross_linux_tree/usr/local/lib/.keep
Commit 4d3391803462433b05a3344e6c37435f725637c4 by Matthew.Arsenault
AMDGPU/GlobalISel: Legalize G_FMAD
Unlike SelectionDAG, treat this as a normally legalizable operation. In
SelectionDAG this is supposed to only ever formed if it's legal, but
I've found that to be restricting. For AMDGPU this is contextually legal
depending on whether denormal flushing is allowed in the use function.
Technically we currently treat the denormal mode as a subtarget feature,
so custom lowering could be avoided. However I consider this to be a
defect, and this should be contextually dependent on the controllable
rounding mode of the parent function.
llvm-svn: 371800
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h