SuccessChanges

Summary

  1. Improve readability of CXX method overrides list Summary: Separate CXX method overrides list entries with commas. Reviewers: lhames Reviewed By: lhames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35800
  2. [AArch64] Tie source and destination operands for AESMC/AESIMC. Summary: Most CPUs implementing AES fusion require instruction pairs of the form AESE Vn, _ AESMC Vn, Vn and AESD Vn, _ AESIMC Vn, Vn The constraint is added to AES(I)MC instructions which use the result of an AES(E|D) instruction by using AES(I)MCTrr pseudo instructions, which constraint source and destination registers to be the same. A nice side effect of this change is that now all possible pairs are scheduled back-to-back on the exynos-m1 for the misched-fusion-aes.ll test case. I had to update aes_load_store. The version I added initially was very reduced and with the new constraint, AESE/AESMC could not be scheduled back-to-back. I updated the test to be more realistic and still expose the same scheduling problem as the initial test case. Reviewers: t.p.northover, rengolin, evandro, kristof.beyls, silviu.baranga Reviewed By: t.p.northover, evandro Subscribers: aemerson, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D35299
  3. [AArch64] Use 8 bytes as preferred function alignment on Cortex-A53. Summary: This change gives a 0.25% speedup on execution time, a 0.82% improvement in benchmark scores and a 0.20% increase in binary size on a Cortex-A53. These numbers are the geomean results on a wide range of benchmarks from the test-suite and a range of proprietary suites. Reviewers: t.p.northover, aadg, silviu.baranga, mcrosier, rengolin Reviewed By: rengolin Subscribers: grimar, davide, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35568
  4. MC: simplify internal function call parameter Rather than passing along most of the parameters, pass a reference to the MCDWARFrameInfo instead. This makes it easier to pass additional information about the frame to the checks. We need to keep the extra constructor for the Key around to allow the construction of the null and tombstone keys. NFC.
  5. MC: account for the return column in the CIE key If the return column is different, we cannot coalesce the CIE across the FDEs. Add that to the key calculation. This ensures that we emit a separate CIE.
Revision 309496 by lll:
Improve readability of CXX method overrides list

Summary:
Separate CXX method overrides list entries with commas.

Reviewers: lhames

Reviewed By: lhames

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35800
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/AST/ASTDumper.cppclang.src/lib/AST/ASTDumper.cpp
Revision 309495 by fhahn:
[AArch64] Tie source and destination operands for AESMC/AESIMC.

Summary:
Most CPUs implementing AES fusion require instruction pairs of the form
    AESE Vn, _
    AESMC Vn, Vn
and
    AESD Vn, _
    AESIMC Vn, Vn

The constraint is added to AES(I)MC instructions which use the result of
an AES(E|D) instruction by using AES(I)MCTrr pseudo instructions, which
constraint source and destination registers to be the same.

A nice side effect of this change is that now all possible pairs are
scheduled back-to-back on the exynos-m1 for the misched-fusion-aes.ll
test case.

I had to update aes_load_store. The version I added initially was very
reduced and with the new constraint, AESE/AESMC could not be scheduled
back-to-back. I updated the test to be more realistic and still expose
the same scheduling problem as the initial test case.

Reviewers: t.p.northover, rengolin, evandro, kristof.beyls, silviu.baranga

Reviewed By: t.p.northover, evandro

Subscribers: aemerson, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D35299
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cppllvm.src/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.tdllvm.src/lib/Target/AArch64/AArch64InstrInfo.td
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64MacroFusion.cppllvm.src/lib/Target/AArch64/AArch64MacroFusion.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/misched-fusion-aes.llllvm.src/test/CodeGen/AArch64/misched-fusion-aes.ll
The file was modified/llvm/trunk/test/MC/AArch64/arm64-crypto.sllvm.src/test/MC/AArch64/arm64-crypto.s
Revision 309494 by fhahn:
[AArch64] Use 8 bytes as preferred function alignment on Cortex-A53.

Summary:
This change gives a 0.25% speedup on execution time, a 0.82% improvement
in benchmark scores and a 0.20% increase in binary size on a Cortex-A53.
These numbers are the geomean results on a wide range of benchmarks from
the test-suite and a range of proprietary suites.

Reviewers: t.p.northover, aadg, silviu.baranga, mcrosier, rengolin

Reviewed By: rengolin

Subscribers: grimar, davide, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D35568
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cppllvm.src/lib/Target/AArch64/AArch64Subtarget.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/preferred-function-alignment.llllvm.src/test/CodeGen/AArch64/preferred-function-alignment.ll
Revision 309493 by Saleem Abdulrasool:
MC: simplify internal function call parameter

Rather than passing along most of the parameters, pass a reference to
the MCDWARFrameInfo instead.  This makes it easier to pass additional
information about the frame to the checks.  We need to keep the extra
constructor for the Key around to allow the construction of the null and
tombstone keys.  NFC.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/MC/MCDwarf.cppllvm.src/lib/MC/MCDwarf.cpp
Revision 309492 by Saleem Abdulrasool:
MC: account for the return column in the CIE key

If the return column is different, we cannot coalesce the CIE across the
FDEs.  Add that to the key calculation.  This ensures that we emit a
separate CIE.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/MC/MCDwarf.cppllvm.src/lib/MC/MCDwarf.cpp
The file was modified/llvm/trunk/test/Assembler/return-column.sllvm.src/test/Assembler/return-column.s