SuccessChanges

Summary

  1. [X86] Added missing cpu to fix generic scheduling model tests
  2. [InstCombine] Remove explicit check for impossible condition. Replace with assert Summary: As far as I can tell the earlier call getLimitedValue will guaranteed ShiftAmt is saturated to BitWidth-1 preventing it from ever being equal or greater than BitWidth. At one point in the past the getLimitedValue call was only passed BitWidth not BitWidth - 1. This would have allowed the equality case to get here. And in fact this check was initially added as just BitWidth == ShiftAmt, but was changed shortly after to include > which should have never been possible. Reviewers: spatel, majnemer, davide Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36123
  3. [Tooling] Add LLVM_NODISCARD to Replacements::merge Summary: This patch adds LLVM_NODISCARD to Replacements::merge. I've hit this several times already. Reviewers: ioeric Reviewed By: ioeric Subscribers: klimek, cfe-commits Differential Revision: https://reviews.llvm.org/D36149
  4. [globalisel][tablegen] Removed unnecessary typedef pointed out in post-commit review for r308599. NFC
  5. DebugInfo: Update flag description that'd been copypasted from another Post-commit review feedback from Paul Robinson on r309630. Thanks Paul!
  6. [PostDom] document the current handling of infinite loops and unreachables Summary: As we are in the process of changing the behavior of how the post-dominator tree is computed, make sure we have some more test coverage in this area. Current inconsistencies: - Newly unreachable nodes are not added as new roots, in case the PDT is updated but not rebuilt. - Newly unreachable loops are not added to the CFG at all (neither when building from scratch nor when updating the CFG). This is inconsistent with the fact that unreachables are added to the PDT, but unreachable loops not. On the other side, PDT relationships are not loosened at the moment in cases where new unreachable loops are built. This commit is providing additional test coverage for https://reviews.llvm.org/D35851 Reviewers: dberlin, kuhar Reviewed By: kuhar Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36107
  7. [DebugInfo] Use shrink_to_fit to simplify code. NFCI.
  8. [DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector. Summary: Allow SCALAR_TO_VECTOR of EXTRACT_VECTOR_ELT to reduce to EXTRACT_SUBVECTOR of vector shuffle when output is smaller. Marginally improves vector shuffle computations. Reviewers: efriedma, RKSimon, spatel Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D35566
  9. [Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359
  10. [OpenCL] Add missing subgroup builtins This adds get_kernel_max_sub_group_size_for_ndrange and get_kernel_sub_group_count_for_ndrange.
  11. [Hexagon] Convert HVX vector constants of i1 to i8 Certain operations require vector of i1 values. However, for Hexagon architecture compatibility, they need to be represented as vector of i8. Patch by Suyog Sarda.
  12. [X86] Regenerate big structure return test and check on x86_64 as well.
  13. AMDGPU/GlobalISel: Add support for amdgpu_vs calling convention Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D35916
Revision 309691 by rksimon:
[X86] Added missing cpu to fix generic scheduling model tests
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/avx-schedule.llllvm.src/test/CodeGen/X86/avx-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx2-schedule.llllvm.src/test/CodeGen/X86/avx2-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/bmi-schedule.llllvm.src/test/CodeGen/X86/bmi-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/bmi2-schedule.llllvm.src/test/CodeGen/X86/bmi2-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/f16c-schedule.llllvm.src/test/CodeGen/X86/f16c-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/lzcnt-schedule.llllvm.src/test/CodeGen/X86/lzcnt-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/popcnt-schedule.llllvm.src/test/CodeGen/X86/popcnt-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sse-schedule.llllvm.src/test/CodeGen/X86/sse-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sse2-schedule.llllvm.src/test/CodeGen/X86/sse2-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sse3-schedule.llllvm.src/test/CodeGen/X86/sse3-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sse41-schedule.llllvm.src/test/CodeGen/X86/sse41-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sse42-schedule.llllvm.src/test/CodeGen/X86/sse42-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sse4a-schedule.llllvm.src/test/CodeGen/X86/sse4a-schedule.ll
The file was modified/llvm/trunk/test/CodeGen/X86/ssse3-schedule.llllvm.src/test/CodeGen/X86/ssse3-schedule.ll
Revision 309690 by ctopper:
[InstCombine] Remove explicit check for impossible condition. Replace with assert

Summary:
As far as I can tell the earlier call getLimitedValue will guaranteed ShiftAmt is saturated to BitWidth-1 preventing it from ever being equal or greater than BitWidth.

At one point in the past the getLimitedValue call was only passed BitWidth not BitWidth - 1. This would have allowed the equality case to get here. And in fact this check was initially added as just BitWidth == ShiftAmt, but was changed shortly after to include > which should have never been possible.

Reviewers: spatel, majnemer, davide

Reviewed By: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36123
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cppllvm.src/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Revision 309689 by krasimir:
[Tooling] Add LLVM_NODISCARD to Replacements::merge

Summary:
This patch adds LLVM_NODISCARD to Replacements::merge. I've hit this
several times already.

Reviewers: ioeric

Reviewed By: ioeric

Subscribers: klimek, cfe-commits

Differential Revision: https://reviews.llvm.org/D36149
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Tooling/Core/Replacement.hclang.src/include/clang/Tooling/Core/Replacement.h
Revision 309687 by dsanders:
[globalisel][tablegen] Removed unnecessary typedef pointed out in post-commit review for r308599. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.hllvm.src/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
Revision 309685 by dblaikie:
DebugInfo: Update flag description that'd been copypasted from another

Post-commit review feedback from Paul Robinson on r309630. Thanks Paul!
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cppllvm.src/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Revision 309684 by grosser:
[PostDom] document the current handling of infinite loops and unreachables

Summary:
As we are in the process of changing the behavior of how the post-dominator tree
is computed, make sure we have some more test coverage in this area.

Current inconsistencies:

  - Newly unreachable nodes are not added as new roots, in case the PDT is updated
    but not rebuilt.

  - Newly unreachable loops are not added to the CFG at all (neither when
    building from scratch nor when updating the CFG). This is inconsistent with
    the fact that unreachables are added to the PDT, but unreachable loops not.
    On the other side, PDT relationships are not loosened at the moment in
    cases where new unreachable loops are built.

This commit is providing additional test coverage for
https://reviews.llvm.org/D35851

Reviewers: dberlin, kuhar

Reviewed By: kuhar

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36107
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/unittests/IR/DominatorTreeTest.cppllvm.src/unittests/IR/DominatorTreeTest.cpp
Revision 309683 by d0k:
[DebugInfo] Use shrink_to_fit to simplify code. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFDebugAranges.cppllvm.src/lib/DebugInfo/DWARF/DWARFDebugAranges.cpp
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFUnit.cppllvm.src/lib/DebugInfo/DWARF/DWARFUnit.cpp
Revision 309680 by niravd:
[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.

Summary:
Allow SCALAR_TO_VECTOR of EXTRACT_VECTOR_ELT to reduce to
EXTRACT_SUBVECTOR of vector shuffle when output is smaller. Marginally
improves vector shuffle computations.

Reviewers: efriedma, RKSimon, spatel

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D35566
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/arm64-neon-copy.llllvm.src/test/CodeGen/AArch64/arm64-neon-copy.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/neon-scalar-copy.llllvm.src/test/CodeGen/AArch64/neon-scalar-copy.ll
Revision 309679 by spetrovic:
[Mips] Fix for BBIT octeon instruction

This patch enables control flow optimization for
variations of BBIT instruction. In this case
optimization removes unnecessary branch after
BBIT instruction.

Differential Revision: https://reviews.llvm.org/D35359
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cppllvm.src/lib/Target/Mips/MipsSEInstrInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/Mips/octeon.llllvm.src/test/CodeGen/Mips/octeon.ll
Revision 309678 by joey:
[OpenCL] Add missing subgroup builtins

This adds get_kernel_max_sub_group_size_for_ndrange and
get_kernel_sub_group_count_for_ndrange.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/Builtins.defclang.src/include/clang/Basic/Builtins.def
The file was modified/cfe/trunk/lib/CodeGen/CGBuiltin.cppclang.src/lib/CodeGen/CGBuiltin.cpp
The file was modified/cfe/trunk/lib/Sema/SemaChecking.cppclang.src/lib/Sema/SemaChecking.cpp
The file was modified/cfe/trunk/test/CodeGenOpenCL/cl20-device-side-enqueue.clclang.src/test/CodeGenOpenCL/cl20-device-side-enqueue.cl
The file was modified/cfe/trunk/test/SemaOpenCL/cl20-device-side-enqueue.clclang.src/test/SemaOpenCL/cl20-device-side-enqueue.cl
Revision 309677 by kparzysz:
[Hexagon] Convert HVX vector constants of i1 to i8

Certain operations require vector of i1 values. However, for Hexagon
architecture compatibility, they need to be represented as vector of i8.

Patch by Suyog Sarda.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cppllvm.src/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was added/llvm/trunk/test/CodeGen/Hexagon/convert_const_i1_to_i8.llllvm.src/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
Revision 309676 by rksimon:
[X86] Regenerate big structure return test and check on x86_64 as well.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/bigstructret.llllvm.src/test/CodeGen/X86/bigstructret.ll
Revision 309675 by tstellar:
AMDGPU/GlobalISel: Add support for amdgpu_vs calling convention

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D35916
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cppllvm.src/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll