SuccessChanges

Summary

  1. [PM] Fix a bug where through CGSCC iteration we can get infinite-inlining across multiple runs of the inliner by keeping a tiny history of internal-to-SCC inlining decisions. This is still a bit gross, but I don't yet have any fundamentally better ideas and numerous people are blocked on this to use new PM and ThinLTO together. The core of the idea is to detect when we are about to do an inline that has a chance of re-splitting an SCC which we have split before with a similar inlining step. That is a critical component in the inlining forming a cycle and so far detects all of the various cyclic patterns I can come up with as well as the original real-world test case (which comes from a ThinLTO build of libunwind). I've added some tests that I think really demonstrate what is going on here. They are essentially state machines that march the inliner through various steps of a cycle and check that we stop when the cycle is closed and that we actually did do inlining to form that cycle. A lot of thanks go to Eric Christopher and Sanjoy Das for the help understanding this issue and improving the test cases. The biggest "yuck" here is the layering issue -- the CGSCC pass manager is providing somewhat magical state to the inliner for it to use to make itself converge. This isn't great, but I don't honestly have a lot of better ideas yet and at least seems nicely isolated. I have tested this patch, and it doesn't block *any* inlining on the entire LLVM test suite and SPEC, so it seems sufficiently narrowly targeted to the issue at hand. We have come up with hypothetical issues that this patch doesn't cover, but so far none of them are practical and we don't have a viable solution yet that covers the hypothetical stuff, so proceeding here in the interim. Definitely an area that we will be back and revisiting in the future. Differential Revision: https://reviews.llvm.org/D36188
  2. AMDGPU: Fix clobbering CSR VGPRs when spilling SGPR to it
  3. AMDGPU: Fix emitting encoded calls This was failing on out of bounds access to the extra operands on the s_swappc_b64 beyond those in the instruction definition. This was working, but somehow regressed within the past few weeks, although I don't see any obvious commit.
  4. AMDGPU: Analyze callee resource usage in AsmPrinter
  5. Update the new PM pipeline to make ICP aware if it is SamplePGO build. Summary: In ThinLTO backend compile, OPTOptions are not set so that the ICP in ThinLTO backend does not know if it is a SamplePGO build, in which profile count needs to be annotated directly on call instructions. This patch cleaned up the PGOOptions handling logic and passes down PGOOptions to ThinLTO backend. Reviewers: chandlerc, tejohnson, davidxl Reviewed By: chandlerc Subscribers: sanjoy, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D36052
  6. [AMDGPU] Fix asan error after last commit Previous change "Turn s_and_saveexec_b64 into s_and_b64 if result is unused" introduced asan use-after-poison error. Instruction was analyzed after eraseFromParent() calls. Move analysys higher than erase.
  7. [Driver] Disable static C++ library support on Fuchsia Don't support or build static C++ libraries for Fuchsia. Differential Revision: https://reviews.llvm.org/D36202
  8. [DAG] Refactor store merge subexpressions. NFC. Distribute various expressions across ifs.
  9. AMDGPU: Don't place arguments in emergency stack slot When finding the fixed offsets for function arguments, this needs to skip over the 4 bytes reserved for the emergency stack slot.
  10. DAG: Undo and->or combine with FrameIndexes This pattern shows up when lowering byval copies on AMDGPU. The byval object access is split into 4-byte chunks, adding a constant offset to the FixedStack base. When some of the offsets turn into ors, this prevents combining the constant offsets. This makes it not apparent that the object is there when matching addressing modes, so it ends up using a scratch wave offset relative access and the lengthy frame index expansion for that.
  11. X86: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287
  12. Update LiveDebugValues to generate DIExpressions for spill offsets instead of using the deprecated offset field of DBG_VALUE. This has no observable effect on the generated DWARF, but the assembler comments will look different. rdar://problem/33580047
  13. Revert "Reland "[llvm][llvm-objcopy] Added support for outputting to binary in llvm-objcopy"" This is failing to compile on 32-bit ARM bots. This reverts commit r309768.
  14. Update MIR testcase to reflect change in r309751. rdar://problem/33580047
  15. Reland "[llvm][llvm-objcopy] Added support for outputting to binary in llvm-objcopy" This change adds the "-O binary" flag which directs llvm-objcopy to output the object file to the same format as GNU objcopy does when given the flag "-O binary". This was done by splitting the Object class into two subclasses ObjectELF and ObjectBianry which each output a different format but relay on the same code to read in the Object in Object. Patch by Jake Ehrlich Differential Revision: https://reviews.llvm.org/D34480
  16. [AMDGPU] Turn s_and_saveexec_b64 into s_and_b64 if result is unused With SI_END_CF elimination for some nested control flow we can now eliminate saved exec register completely by turning a saveexec version of instruction into just a logical instruction. Differential Revision: https://reviews.llvm.org/D36007
  17. Remove unused accessor (NFC) rdar://problem/33580047
  18. [AMDGPU] Collapse adjacent SI_END_CF Add a pass to remove redundant S_OR_B64 instructions enabling lanes in the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any vector instructions between them we can only keep outer SI_END_CF, given that CFG is structured and exec bits of the outer end statement are always not less than exec bit of the inner one. This needs to be done before the RA to eliminate saved exec bits registers but after register coalescer to have no vector registers copies in between of different end cf statements. Differential Revision: https://reviews.llvm.org/D35967
  19. Assert that the offset of a MachineLocation is always 0. This is to convince me that it may safely be removed in a follow-up commit. rdar://problem/33580047
  20. [sanitizer_common] Fuchsia-specific symbolizer Summary: Fuchsia doesn't support built-in symbolization per se at all. Instead, it always emits a Fuchsia-standard "symbolizer markup" format that makes it possible for a post-processing filter to massage the logs into symbolized format. Hence, it does not support user-specified formatting options for backtraces or other symbolization. Reviewers: vitalybuka, alekseyshl, kcc Subscribers: kubamracek, mgorny, phosek, filcab, llvm-commits Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D36032
  21. [SCEV/IndVars] Always compute loop exiting values if the backedge count is 0 If SCEV can prove that the backedge taken count for a loop is zero, it does not need to "understand" a recursive PHI to compute its exiting value. This should fix PR33885.
  22. Use helper function instead of manually constructing DBG_VALUEs (NFC) rdar://problem/33580047
Revision 309784 by chandlerc:
[PM] Fix a bug where through CGSCC iteration we can get
infinite-inlining across multiple runs of the inliner by keeping a tiny
history of internal-to-SCC inlining decisions.

This is still a bit gross, but I don't yet have any fundamentally better
ideas and numerous people are blocked on this to use new PM and ThinLTO
together.

The core of the idea is to detect when we are about to do an inline that
has a chance of re-splitting an SCC which we have split before with
a similar inlining step. That is a critical component in the inlining
forming a cycle and so far detects all of the various cyclic patterns
I can come up with as well as the original real-world test case (which
comes from a ThinLTO build of libunwind).

I've added some tests that I think really demonstrate what is going on
here. They are essentially state machines that march the inliner through
various steps of a cycle and check that we stop when the cycle is closed
and that we actually did do inlining to form that cycle.

A lot of thanks go to Eric Christopher and Sanjoy Das for the help
understanding this issue and improving the test cases.

The biggest "yuck" here is the layering issue -- the CGSCC pass manager
is providing somewhat magical state to the inliner for it to use to make
itself converge. This isn't great, but I don't honestly have a lot of
better ideas yet and at least seems nicely isolated.

I have tested this patch, and it doesn't block *any* inlining on the
entire LLVM test suite and SPEC, so it seems sufficiently narrowly
targeted to the issue at hand.

We have come up with hypothetical issues that this patch doesn't cover,
but so far none of them are practical and we don't have a viable
solution yet that covers the hypothetical stuff, so proceeding here in
the interim. Definitely an area that we will be back and revisiting in
the future.

Differential Revision: https://reviews.llvm.org/D36188
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Analysis/CGSCCPassManager.hllvm.src/include/llvm/Analysis/CGSCCPassManager.h
The file was modified/llvm/trunk/lib/Transforms/IPO/Inliner.cppllvm.src/lib/Transforms/IPO/Inliner.cpp
The file was added/llvm/trunk/test/Transforms/Inline/cgscc-cycle.llllvm.src/test/Transforms/Inline/cgscc-cycle.ll
Revision 309783 by arsenm:
AMDGPU: Fix clobbering CSR VGPRs when spilling SGPR to it
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cppllvm.src/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cppllvm.src/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.hllvm.src/lib/Target/AMDGPU/SIMachineFunctionInfo.h
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/byval-frame-setup.llllvm.src/test/CodeGen/AMDGPU/byval-frame-setup.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/call-graph-register-usage.llllvm.src/test/CodeGen/AMDGPU/call-graph-register-usage.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/callee-frame-setup.llllvm.src/test/CodeGen/AMDGPU/callee-frame-setup.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/nested-calls.llllvm.src/test/CodeGen/AMDGPU/nested-calls.ll
Revision 309782 by arsenm:
AMDGPU: Fix emitting encoded calls

This was failing on out of bounds access to the extra operands
on the s_swappc_b64 beyond those in the instruction definition.

This was working, but somehow regressed within the past few weeks,
although I don't see any obvious commit.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cppllvm.src/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cppllvm.src/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/call-encoding.llllvm.src/test/CodeGen/AMDGPU/call-encoding.ll
Revision 309781 by arsenm:
AMDGPU: Analyze callee resource usage in AsmPrinter
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cppllvm.src/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cppllvm.src/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cppllvm.src/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cppllvm.src/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.tdllvm.src/lib/Target/AMDGPU/SIInstructions.td
The file was added/llvm/trunk/test/CodeGen/AMDGPU/call-graph-register-usage.llllvm.src/test/CodeGen/AMDGPU/call-graph-register-usage.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/promote-alloca-calling-conv.llllvm.src/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
Revision 309780 by dehao:
Update the new PM pipeline to make ICP aware if it is SamplePGO build.

Summary: In ThinLTO backend compile, OPTOptions are not set so that the ICP in ThinLTO backend does not know if it is a SamplePGO build, in which profile count needs to be annotated directly on call instructions. This patch cleaned up the PGOOptions handling logic and passes down PGOOptions to ThinLTO backend.

Reviewers: chandlerc, tejohnson, davidxl

Reviewed By: chandlerc

Subscribers: sanjoy, llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D36052
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/LTO/LTOBackend.cppllvm.src/lib/LTO/LTOBackend.cpp
The file was modified/llvm/trunk/lib/Passes/PassBuilder.cppllvm.src/lib/Passes/PassBuilder.cpp
The file was added/llvm/trunk/test/LTO/Resolution/X86/Inputs/load-sample-prof-icp.profllvm.src/test/LTO/Resolution/X86/Inputs/load-sample-prof-icp.prof
The file was added/llvm/trunk/test/LTO/Resolution/X86/load-sample-prof-icp.llllvm.src/test/LTO/Resolution/X86/load-sample-prof-icp.ll
Revision 309779 by rampitec:
[AMDGPU] Fix asan error after last commit

Previous change "Turn s_and_saveexec_b64 into s_and_b64 if
result is unused" introduced asan use-after-poison error.
Instruction was analyzed after eraseFromParent() calls.

Move analysys higher than erase.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cppllvm.src/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
Revision 309778 by phosek:
[Driver] Disable static C++ library support on Fuchsia

Don't support or build static C++ libraries for Fuchsia.

Differential Revision: https://reviews.llvm.org/D36202
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/cmake/caches/Fuchsia-stage2.cmakeclang.src/cmake/caches/Fuchsia-stage2.cmake
The file was modified/cfe/trunk/lib/Driver/ToolChains/Fuchsia.cppclang.src/lib/Driver/ToolChains/Fuchsia.cpp
The file was modified/cfe/trunk/test/Driver/fuchsia.cppclang.src/test/Driver/fuchsia.cpp
Revision 309777 by niravd:
[DAG] Refactor store merge subexpressions. NFC.

Distribute various expressions across ifs.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Revision 309776 by arsenm:
AMDGPU: Don't place arguments in emergency stack slot

When finding the fixed offsets for function arguments,
this needs to skip over the 4 bytes reserved for the
emergency stack slot.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cppllvm.src/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/byval-frame-setup.llllvm.src/test/CodeGen/AMDGPU/byval-frame-setup.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.llllvm.src/test/CodeGen/AMDGPU/call-argument-types.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.llllvm.src/test/CodeGen/AMDGPU/frame-index-elimination.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/function-args.llllvm.src/test/CodeGen/AMDGPU/function-args.ll
Revision 309775 by arsenm:
DAG: Undo and->or combine with FrameIndexes

This pattern shows up when lowering byval copies on AMDGPU.

The byval object access is split into 4-byte chunks, adding a
constant offset to the FixedStack base. When some of the offsets
turn into ors, this prevents combining the constant offsets.

This makes it not apparent that the object is there when matching
addressing modes, so it ends up using a scratch wave offset
relative access and the lengthy frame index expansion for that.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.llllvm.src/test/CodeGen/AArch64/arm64-abi-varargs.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/byval-frame-setup.llllvm.src/test/CodeGen/AMDGPU/byval-frame-setup.ll
The file was modified/llvm/trunk/test/CodeGen/BPF/undef.llllvm.src/test/CodeGen/BPF/undef.ll
Revision 309774 by matze:
X86: Do not use llc -march in tests.

`llc -march` is problematic because it only switches the target
architecture, but leaves the operating system unchanged. This
occasionally leads to indeterministic tests because the OS from
LLVM_DEFAULT_TARGET_TRIPLE is used.

However we can simply always use `llc -mtriple` instead. This changes
all the tests to do this to avoid people using -march when they copy and
paste parts of tests.

See also the discussion in https://reviews.llvm.org/D35287
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.llllvm.src/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2003-08-23-DeadBlockTest.llllvm.src/test/CodeGen/X86/2003-08-23-DeadBlockTest.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2003-11-03-GlobalBool.llllvm.src/test/CodeGen/X86/2003-11-03-GlobalBool.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2004-02-13-FrameReturnAddress.llllvm.src/test/CodeGen/X86/2004-02-13-FrameReturnAddress.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2004-02-14-InefficientStackPointer.llllvm.src/test/CodeGen/X86/2004-02-14-InefficientStackPointer.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2004-02-22-Casts.llllvm.src/test/CodeGen/X86/2004-02-22-Casts.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2004-03-30-Select-Max.llllvm.src/test/CodeGen/X86/2004-03-30-Select-Max.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2004-04-13-FPCMOV-Crash.llllvm.src/test/CodeGen/X86/2004-04-13-FPCMOV-Crash.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2004-06-10-StackifierCrash.llllvm.src/test/CodeGen/X86/2004-06-10-StackifierCrash.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2004-10-08-SelectSetCCFold.llllvm.src/test/CodeGen/X86/2004-10-08-SelectSetCCFold.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2005-01-17-CycleInDAG.llllvm.src/test/CodeGen/X86/2005-01-17-CycleInDAG.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2005-02-14-IllegalAssembler.llllvm.src/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2005-05-08-FPStackifierPHI.llllvm.src/test/CodeGen/X86/2005-05-08-FPStackifierPHI.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-03-02-InstrSchedBug.llllvm.src/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-04-04-CrossBlockCrash.llllvm.src/test/CodeGen/X86/2006-04-04-CrossBlockCrash.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-04-27-ISelFoldingBug.llllvm.src/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-05-01-SchedCausingSpills.llllvm.src/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-05-02-InstrSched2.llllvm.src/test/CodeGen/X86/2006-05-02-InstrSched2.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.llllvm.src/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-05-08-InstrSched.llllvm.src/test/CodeGen/X86/2006-05-08-InstrSched.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.llllvm.src/test/CodeGen/X86/2006-05-11-InstrSched.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-05-17-VectorArg.llllvm.src/test/CodeGen/X86/2006-05-17-VectorArg.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.llllvm.src/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-05-25-CycleInDAG.llllvm.src/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-07-10-InlineAsmAConstraint.llllvm.src/test/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.llllvm.src/test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-07-20-InlineAsm.llllvm.src/test/CodeGen/X86/2006-07-20-InlineAsm.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.llllvm.src/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-07-31-SingleRegClass.llllvm.src/test/CodeGen/X86/2006-07-31-SingleRegClass.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-08-07-CycleInDAG.llllvm.src/test/CodeGen/X86/2006-08-07-CycleInDAG.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-08-16-CycleInDAG.llllvm.src/test/CodeGen/X86/2006-08-16-CycleInDAG.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-08-21-ExtraMovInst.llllvm.src/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-09-01-CycleInDAG.llllvm.src/test/CodeGen/X86/2006-09-01-CycleInDAG.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-10-09-CycleInDAG.llllvm.src/test/CodeGen/X86/2006-10-09-CycleInDAG.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.llllvm.src/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-10-12-CycleInDAG.llllvm.src/test/CodeGen/X86/2006-10-12-CycleInDAG.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-10-13-CycleInDAG.llllvm.src/test/CodeGen/X86/2006-10-13-CycleInDAG.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.llllvm.src/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-11-12-CSRetCC.llllvm.src/test/CodeGen/X86/2006-11-12-CSRetCC.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.llllvm.src/test/CodeGen/X86/2006-11-17-IllegalMove.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-11-27-SelectLegalize.llllvm.src/test/CodeGen/X86/2006-11-27-SelectLegalize.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-12-16-InlineAsmCrash.llllvm.src/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2006-12-19-IntelSyntax.llllvm.src/test/CodeGen/X86/2006-12-19-IntelSyntax.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2007-01-13-StackPtrIndex.llllvm.src/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2007-01-29-InlineAsm-ir.llllvm.src/test/CodeGen/X86/2007-01-29-InlineAsm-ir.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2007-02-04-OrAddrMode.llllvm.src/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.llllvm.src/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.llllvm.src/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2007-02-25-FastCCStack.llllvm.src/test/CodeGen/X86/2007-02-25-FastCCStack.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.llllvm.src/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2007-03-16-InlineAsm.llllvm.src/test/CodeGen/X86/2007-03-16-InlineAsm.ll
The file was modified/llvm/trunk/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.llllvm.src/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll
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The file was modified/llvm/trunk/test/CodeGen/X86/vshift_split.llllvm.src/test/CodeGen/X86/vshift_split.ll
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The file was modified/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.llllvm.src/test/CodeGen/X86/wide-fma-contraction.ll
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The file was modified/llvm/trunk/test/CodeGen/X86/widen_load-1.llllvm.src/test/CodeGen/X86/widen_load-1.ll
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The file was modified/llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.llllvm.src/test/CodeGen/X86/x86-64-double-shifts-Oz-Os-O2.ll
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The file was modified/llvm/trunk/test/CodeGen/X86/x86-fold-pshufb.llllvm.src/test/CodeGen/X86/x86-fold-pshufb.ll
The file was modified/llvm/trunk/test/CodeGen/X86/x87.llllvm.src/test/CodeGen/X86/x87.ll
The file was modified/llvm/trunk/test/CodeGen/X86/xmm-r64.llllvm.src/test/CodeGen/X86/xmm-r64.ll
The file was modified/llvm/trunk/test/CodeGen/X86/xtest.llllvm.src/test/CodeGen/X86/xtest.ll
The file was modified/llvm/trunk/test/CodeGen/X86/zero-remat.llllvm.src/test/CodeGen/X86/zero-remat.ll
The file was modified/llvm/trunk/test/CodeGen/X86/zext-inreg-0.llllvm.src/test/CodeGen/X86/zext-inreg-0.ll
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The file was modified/llvm/trunk/test/CodeGen/X86/zlib-longest-match.llllvm.src/test/CodeGen/X86/zlib-longest-match.ll
Revision 309773 by Adrian Prantl:
Update LiveDebugValues to generate DIExpressions for spill offsets
instead of using the deprecated offset field of DBG_VALUE.

This has no observable effect on the generated DWARF, but the
assembler comments will look different.

rdar://problem/33580047
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/LiveDebugValues.cppllvm.src/lib/CodeGen/LiveDebugValues.cpp
The file was modified/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-spill.mirllvm.src/test/DebugInfo/MIR/X86/live-debug-values-spill.mir
Revision 309771 by phosek:
Revert "Reland "[llvm][llvm-objcopy] Added support for outputting to binary in llvm-objcopy""

This is failing to compile on 32-bit ARM bots.

This reverts commit r309768.
Change TypePath in RepositoryPath in Workspace
The file was removed/llvm/trunk/test/tools/llvm-objcopy/basic-align-copy.testllvm.src/test/tools/llvm-objcopy/basic-align-copy.test
The file was removed/llvm/trunk/test/tools/llvm-objcopy/basic-binary-copy.testllvm.src/test/tools/llvm-objcopy/basic-binary-copy.test
The file was modified/llvm/trunk/tools/llvm-objcopy/LLVMBuild.txtllvm.src/tools/llvm-objcopy/LLVMBuild.txt
The file was modified/llvm/trunk/tools/llvm-objcopy/Object.cppllvm.src/tools/llvm-objcopy/Object.cpp
The file was modified/llvm/trunk/tools/llvm-objcopy/Object.hllvm.src/tools/llvm-objcopy/Object.h
The file was modified/llvm/trunk/tools/llvm-objcopy/llvm-objcopy.cppllvm.src/tools/llvm-objcopy/llvm-objcopy.cpp
Revision 309769 by Adrian Prantl:
Update MIR testcase to reflect change in r309751.

rdar://problem/33580047
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/DebugInfo/MIR/AArch64/clobber-sp.mirllvm.src/test/DebugInfo/MIR/AArch64/clobber-sp.mir
Revision 309768 by phosek:
Reland "[llvm][llvm-objcopy] Added support for outputting to binary in llvm-objcopy"

This change adds the "-O binary" flag which directs llvm-objcopy to
output the object file to the same format as GNU objcopy does when given
the flag "-O binary". This was done by splitting the Object class into
two subclasses ObjectELF and ObjectBianry which each output a different
format but relay on the same code to read in the Object in Object.

Patch by Jake Ehrlich

Differential Revision: https://reviews.llvm.org/D34480
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/tools/llvm-objcopy/basic-align-copy.testllvm.src/test/tools/llvm-objcopy/basic-align-copy.test
The file was added/llvm/trunk/test/tools/llvm-objcopy/basic-binary-copy.testllvm.src/test/tools/llvm-objcopy/basic-binary-copy.test
The file was modified/llvm/trunk/tools/llvm-objcopy/LLVMBuild.txtllvm.src/tools/llvm-objcopy/LLVMBuild.txt
The file was modified/llvm/trunk/tools/llvm-objcopy/Object.cppllvm.src/tools/llvm-objcopy/Object.cpp
The file was modified/llvm/trunk/tools/llvm-objcopy/Object.hllvm.src/tools/llvm-objcopy/Object.h
The file was modified/llvm/trunk/tools/llvm-objcopy/llvm-objcopy.cppllvm.src/tools/llvm-objcopy/llvm-objcopy.cpp
Revision 309766 by rampitec:
[AMDGPU] Turn s_and_saveexec_b64 into s_and_b64 if result is unused

With SI_END_CF elimination for some nested control flow we can now
eliminate saved exec register completely by turning a saveexec version
of instruction into just a logical instruction.

Differential Revision: https://reviews.llvm.org/D36007
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cppllvm.src/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cppllvm.src/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/collapse-endcf.llllvm.src/test/CodeGen/AMDGPU/collapse-endcf.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/reduce-saveexec.mirllvm.src/test/CodeGen/AMDGPU/reduce-saveexec.mir
Revision 309763 by Adrian Prantl:
Remove unused accessor (NFC)

rdar://problem/33580047
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/MC/MachineLocation.hllvm.src/include/llvm/MC/MachineLocation.h
Revision 309762 by rampitec:
[AMDGPU] Collapse adjacent SI_END_CF

Add a pass to remove redundant S_OR_B64 instructions enabling lanes in
the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any
vector instructions between them we can only keep outer SI_END_CF, given
that CFG is structured and exec bits of the outer end statement are always
not less than exec bit of the inner one.

This needs to be done before the RA to eliminate saved exec bits registers
but after register coalescer to have no vector registers copies in between
of different end cf statements.

Differential Revision: https://reviews.llvm.org/D35967
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPU.hllvm.src/lib/Target/AMDGPU/AMDGPU.h
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cppllvm.src/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/CMakeLists.txtllvm.src/lib/Target/AMDGPU/CMakeLists.txt
The file was added/llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cppllvm.src/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/collapse-endcf.llllvm.src/test/CodeGen/AMDGPU/collapse-endcf.ll
Revision 309761 by Adrian Prantl:
Assert that the offset of a MachineLocation is always 0.
This is to convince me that it may safely be removed in a follow-up commit.

rdar://problem/33580047
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/MC/MachineLocation.hllvm.src/include/llvm/MC/MachineLocation.h
Revision 309760 by Vitaly Buka:
[sanitizer_common] Fuchsia-specific symbolizer

Summary:
Fuchsia doesn't support built-in symbolization per se at all.
Instead, it always emits a Fuchsia-standard "symbolizer markup"
format that makes it possible for a post-processing filter to
massage the logs into symbolized format.  Hence, it does not
support user-specified formatting options for backtraces or other
symbolization.

Reviewers: vitalybuka, alekseyshl, kcc

Subscribers: kubamracek, mgorny, phosek, filcab, llvm-commits

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D36032
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/lib/sanitizer_common/CMakeLists.txtcompiler-rt.src/lib/sanitizer_common/CMakeLists.txt
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_stacktrace_printer.cccompiler-rt.src/lib/sanitizer_common/sanitizer_stacktrace_printer.cc
The file was added/compiler-rt/trunk/lib/sanitizer_common/sanitizer_symbolizer_fuchsia.cccompiler-rt.src/lib/sanitizer_common/sanitizer_symbolizer_fuchsia.cc
The file was modified/compiler-rt/trunk/lib/sanitizer_common/sanitizer_symbolizer_libcdep.cccompiler-rt.src/lib/sanitizer_common/sanitizer_symbolizer_libcdep.cc
Revision 309758 by sanjoy:
[SCEV/IndVars] Always compute loop exiting values if the backedge count is 0

If SCEV can prove that the backedge taken count for a loop is zero, it does not
need to "understand" a recursive PHI to compute its exiting value.

This should fix PR33885.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/ScalarEvolution.cppllvm.src/lib/Analysis/ScalarEvolution.cpp
The file was modified/llvm/trunk/test/Transforms/IndVarSimplify/exit_value_test2.llllvm.src/test/Transforms/IndVarSimplify/exit_value_test2.ll
Revision 309757 by Adrian Prantl:
Use helper function instead of manually constructing DBG_VALUEs (NFC)

rdar://problem/33580047
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cppllvm.src/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cppllvm.src/lib/CodeGen/SelectionDAG/FastISel.cpp