SuccessChanges

Summary

  1. [X86] Adding a test for vector shuffle extractions. When both the vector inputs of the shuffle vector is comprising of same vector or shuffle mask is accessing elements from only one operand vector (like in PR33758 test already present). Committed on behalf of @jbhateja (Jatin Bhateja) Differential Revision: https://reviews.llvm.org/D36271
  2. Revert "[AArch64] Simplify AES*Tied pseudo expansion (NFC)." This reverts commit r309821. My suggestion was wrong because it left the MachineOperands tied which confused the verifier. Since there's no easy way to untie operands, the original BuildMI solution is probably best.
  3. [X86][AVX512] Tidied up v64i8 vector shuffle tests with triple
  4. Revert r304836. See discussion in https://reviews.llvm.org/D33900#824172
  5. AMDGPU/SI: Don't fix a PHI under uniform branch in SIFixSGPRCopies only when sources and destination are all sgprs Summary: If a PHI has at lease one VGPR operand, we have to fix the PHI in SIFixSGPRCopies. Reviewer: Matt Differential Revision: http://reviews.llvm.org/D34727
  6. [diagtool] Add ability to pass in the id and return the name for a particular diagnostic. Differential Revision: https://reviews.llvm.org/D36252
  7. Fix use after free in unit test.
  8. [DAG] Allow merging of stores of vector loads Remove restriction disallowing merging of stores vector loads into larger store of larger vector load. Reviewers: RKSimon, efriedma, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36158
  9. Revert r309923, it caused PR34045.
  10. [TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is true Consider the following instruction: "inst.eq $dst, $src" where ".eq" is an optional flag operand. The $src and $dst operands are registers. If we parse the instruction "inst r0, r1", the flag is not present and it will be marked in the "OptionalOperandsMask" variable. After the matching is complete we call the "convertToMCInst" method. The current implementation works only if the optional operands are at the end of the array. The "Operands" array looks like [token:"inst", reg:r0, reg:r1]. The first operand that must be added to the MCInst is the destination, the r0 register. The "OpIdx" (in the Operands array) for this register is 2. However, since the flag is not present in the Operands, the actual index for r0 should be 1. The flag is not present since we rely on the default value. This patch removes the "NumDefaults" variable and replaces it with an array (DefaultsOffset). This array contains an index for each operand (excluding the mnemonic). At each index, the array contains the number of optional operands that should be subtracted. For the previous example, this array looks like this: [0, 1, 1]. When we need to access the r0 register, we compute its index as 2 - DefaultsOffset[1] = 1. Patch by Alexandru Guduleasa! Reviewers: SamWot, nhaustov, niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35998
  11. Fix some typos in the documentation. Patch by: Reka Nikolett Kovacs
  12. [NewGVN] fix typos; NFC
  13. [BDCE] add tests to show invalid/incomplete transforms
Revision 309963 by rksimon:
[X86] Adding a test for vector shuffle extractions.

When both the vector inputs of the shuffle vector is comprising of same vector or shuffle mask is accessing elements from only one operand vector (like in PR33758 test already present).

Committed on behalf of @jbhateja (Jatin Bhateja)

Differential Revision: https://reviews.llvm.org/D36271
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/shuffle-vs-trunc-512.llllvm.src/test/CodeGen/X86/shuffle-vs-trunc-512.ll
Revision 309962 by Tim Northover:
Revert "[AArch64] Simplify AES*Tied pseudo expansion (NFC)."

This reverts commit r309821.

My suggestion was wrong because it left the MachineOperands tied which
confused the verifier. Since there's no easy way to untie operands, the
original BuildMI solution is probably best.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cppllvm.src/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
Revision 309961 by rksimon:
[X86][AVX512] Tidied up v64i8 vector shuffle tests with triple
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v64.llllvm.src/test/CodeGen/X86/vector-shuffle-512-v64.ll
Revision 309960 by nico:
Revert r304836.

See discussion in https://reviews.llvm.org/D33900#824172
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Driver/Driver.cppclang.src/lib/Driver/Driver.cpp
Revision 309959 by chfang:
AMDGPU/SI: Don't fix a PHI under uniform branch in SIFixSGPRCopies only when sources and destination are all sgprs

Summary:
  If a PHI has at lease one VGPR operand, we have to fix the PHI
in SIFixSGPRCopies.

Reviewer:
  Matt

Differential Revision:
  http://reviews.llvm.org/D34727
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cppllvm.src/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/uniform-cfg.llllvm.src/test/CodeGen/AMDGPU/uniform-cfg.ll
Revision 309955 by dhinton:
[diagtool] Add ability to pass in the id and return the name for a
particular diagnostic.

Differential Revision: https://reviews.llvm.org/D36252
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/test/Misc/find-diagnostic-id.cclang.src/test/Misc/find-diagnostic-id.c
The file was modified/cfe/trunk/tools/diagtool/FindDiagnosticID.cppclang.src/tools/diagtool/FindDiagnosticID.cpp
Revision 309952 by d0k:
Fix use after free in unit test.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/unittests/Analysis/ScalarEvolutionTest.cppllvm.src/unittests/Analysis/ScalarEvolutionTest.cpp
Revision 309951 by niravd:
[DAG]  Allow merging of stores of vector loads

Remove restriction disallowing merging of stores vector loads into
larger store of larger vector load.

Reviewers: RKSimon, efriedma, spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36158
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.llllvm.src/test/CodeGen/X86/MergeConsecutiveStores.ll
Revision 309950 by nico:
Revert r309923, it caused PR34045.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.cppllvm.src/lib/Target/ARM/ARMISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.hllvm.src/lib/Target/ARM/ARMISelLowering.h
The file was modified/llvm/trunk/test/CodeGen/ARM/intrinsics-overflow.llllvm.src/test/CodeGen/ARM/intrinsics-overflow.ll
Revision 309949 by niravd:
[TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is true

Consider the following instruction: "inst.eq $dst, $src" where ".eq"
is an optional flag operand.  The $src and $dst operands are
registers.  If we parse the instruction "inst r0, r1", the flag is not
present and it will be marked in the "OptionalOperandsMask" variable.
After the matching is complete we call the "convertToMCInst" method.

The current implementation works only if the optional operands are at
the end of the array.  The "Operands" array looks like [token:"inst",
reg:r0, reg:r1].  The first operand that must be added to the MCInst
is the destination, the r0 register.  The "OpIdx" (in the Operands
array) for this register is 2.  However, since the flag is not present
in the Operands, the actual index for r0 should be 1.  The flag is not
present since we rely on the default value.

This patch removes the "NumDefaults" variable and replaces it with an
array (DefaultsOffset).  This array contains an index for each operand
(excluding the mnemonic).  At each index, the array contains the
number of optional operands that should be subtracted.  For the
previous example, this array looks like this: [0, 1, 1].  When we need
to access the r0 register, we compute its index as 2 -
DefaultsOffset[1] = 1.

Patch by Alexandru Guduleasa!

Reviewers: SamWot, nhaustov, niravd

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35998
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cppllvm.src/utils/TableGen/AsmMatcherEmitter.cpp
Revision 309948 by xazax:
Fix some typos in the documentation.

Patch by: Reka Nikolett Kovacs
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/docs/InternalsManual.rstclang.src/docs/InternalsManual.rst
Revision 309946 by spatel:
[NewGVN] fix typos; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Scalar/NewGVN.cppllvm.src/lib/Transforms/Scalar/NewGVN.cpp
Revision 309945 by spatel:
[BDCE] add tests to show invalid/incomplete transforms
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/Transforms/BDCE/invalidate-assumptions.llllvm.src/test/Transforms/BDCE/invalidate-assumptions.ll