SuccessChanges

Summary

  1. Removing an unused variable that was missed with the refactoring in r310272; NFC.
  2. [AMDGPU] Add pseudo "old" source to all DPP instructions Summary: All instructions with the DPP modifier may not write to certain lanes of the output if bound_ctrl=1 is set or any bits in bank_mask or row_mask aren't set, so the destination register may be both defined and modified. The right way to handle this is to add a constraint that the destination register is the same as one of the inputs. We could tie the destination to the first source, but that would be too restrictive for some use-cases where we want the destination to be some other value before the instruction executes. Instead, add a fake "old" source and tie it to the destination. Effectively, the "old" source defines what value unwritten lanes will get. We'll expose this functionality to users with a new intrinsic later. Also, we want to use DPP instructions for computing derivatives, which means we need to set WQM for them. We also need to enable the entire wavefront when using DPP intrinsics to implement nonuniform subgroup reductions, since otherwise we'll get incorrect results in some cases. To accomodate this, add a new operand to all DPP instructions which will be interpreted by the SI WQM pass. This will be exposed with a new intrinsic later. We'll also add support for Whole Wavefront Mode later. I also fixed llvm.amdgcn.mov.dpp to overwrite the source and fixed up the test. However, I could also keep the old behavior (where lanes that aren't written are undefined) if people want it. Reviewers: tstellar, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D34716
Revision 310285 by aaronballman:
Removing an unused variable that was missed with the refactoring in r310272; NFC.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cppllvm.src/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Revision 310283 by cwabbott:
[AMDGPU] Add pseudo "old" source to all DPP instructions

Summary:
All instructions with the DPP modifier may not write to certain lanes of
the output if bound_ctrl=1 is set or any bits in bank_mask or row_mask
aren't set, so the destination register may be both defined and modified.
The right way to handle this is to add a constraint that the destination
register is the same as one of the inputs. We could tie the destination
to the first source, but that would be too restrictive for some use-cases
where we want the destination to be some other value before the
instruction executes. Instead, add a fake "old" source and tie it to the
destination. Effectively, the "old" source defines what value unwritten
lanes will get. We'll expose this functionality to users with a new
intrinsic later.

Also, we want to use DPP instructions for computing derivatives, which
means we need to set WQM for them. We also need to enable the entire
wavefront when using DPP intrinsics to implement nonuniform subgroup
reductions, since otherwise we'll get incorrect results in some cases.
To accomodate this, add a new operand to all DPP instructions which will
be interpreted by the SI WQM pass. This will be exposed with a new
intrinsic later. We'll also add support for Whole Wavefront Mode later.

I also fixed llvm.amdgcn.mov.dpp to overwrite the source and fixed up
the test. However, I could also keep the old behavior (where lanes that
aren't written are undefined) if people want it.

Reviewers: tstellar, arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D34716
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cppllvm.src/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.tdllvm.src/lib/Target/AMDGPU/SIInstrInfo.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.tdllvm.src/lib/Target/AMDGPU/VOP1Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.tdllvm.src/lib/Target/AMDGPU/VOP2Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOPInstructions.tdllvm.src/lib/Target/AMDGPU/VOPInstructions.td
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/inserted-wait-states.mirllvm.src/test/CodeGen/AMDGPU/inserted-wait-states.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.llllvm.src/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll