SuccessChanges

Summary

  1. [opt-viewer] Use Python 3-compatible iteritems Summary: Replace a usage of a Python 2-specific `dict.iteritems()` with the Python 3-compatible definition provided at the top of the same file. Test Plan: Run `opt-viewer.py` using Python 3 and confirm it no longer encounters a runtime error when calling `dict.iteritems()`. Reviewers: anemet Reviewed By: anemet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36623
  2. [opt-viewer] Use Python 3-compatible `intern()` Summary: In Python 2, `intern()` is a builtin function available to all programs. In Python 3, it was moved into the `sys` module, available as `sys.intern`. Import it such that, within `optrecord.py`, `intern()` is available whether run using Python 2 or 3. Test Plan: Run `opt-viewer.py` using Python 3, confirm it no longer encounters a runtime error when `intern()` is called. Reviewers: anemet Reviewed By: anemet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36622
  3. [AMDGPU] Fix santizer error after last commit Removed useless assert.
  4. Fix typo /NFC
  5. [globalisel][tablegen] Generate TypeObject table. NFC Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085
  6. Update libFuzzer documentation for -fsanitize=fuzzer-no-link flag Differential Revision: https://reviews.llvm.org/D36602
  7. Add -fsanitize=fuzzer-no-link flag to the driver. The flag will perform instrumentation necessary to the fuzzing, but will NOT link libLLVMFuzzer.a library. Necessary when modifying CFLAGS for projects which may produce executables as well as a fuzzable target. Differential Revision: https://reviews.llvm.org/D36600
  8. Enable exceptions for this test case to speculatively fix the build bots. Hopefully corrects: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/15666
  9. [AMDGPU] Ported and adopted AMDLibCalls pass The pass does simplifications of well known AMD library calls. If given -amdgpu-prelink option it works in a pre-link mode which allows to reference new library functions which will be linked in later. In addition it also used to process traditional AMD option -fuse-native which allows to replace some of the functions with their fast native implementations from the library. The necessary glue to pass the prelink option and translate -fuse-native is to be added to the driver. Differential Revision: https://reviews.llvm.org/D36436
  10. Orc: PR33769: Don't rely on comparisons with default constructed iterators
  11. Add hicpp-exception-baseclass to the HIC++ module. This enforces that throwing an exception in C++ requires that exception to inherit from std::exception. Patch by Jonas Toth.
  12. [AVX512] Remove and autoupgrade many of the broadcast intrinsics Summary: This autoupgrades most of the broadcast intrinsics. They've been unused in clang for some time. This leaves the 32x2 intrinsics because they are still used in clang. Reviewers: RKSimon, zvi, igorb Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36606
  13. [x86] Enable some support for lowerVectorShuffleWithUndefHalf with AVX-512 Summary: This teaches 512-bit shuffles to detect unused halfs in order to reduce shuffle size. We may need to refine the 512-bit exit point. I couldn't remember if we had good cross lane shuffles for 8/16 bit with AVX-512 or not. I believe this is step towards being able to handle D36454 without a special case. From here we need to improve our ability to combine extract_subvector with insert_subvector and other extract_subvectors. And we need to support narrowing binary operations where we don't demand all elements. This may be improvements to DAGCombiner::narrowExtractedVectorBinOp(by recognizing an insert_subvector in addition to concat) or we may need a target specific combiner. Reviewers: RKSimon, zvi, delena, jbhateja Reviewed By: RKSimon, jbhateja Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36601
  14. [OpenMP] Enable previously successful offloading tests. Create a separate test file to contain all tests for OpenMP offloading to GPUs. Make libdevice checking more robust by accounting for the case in which no libdevice is found. This changes are in connrection with diff: D29660
  15. [x86] use more shift or LEA for select-of-constants (2nd try) The previous rev (r310208) failed to account for overflow when subtracting the constants to see if they're suitable for shift/lea. This version add a check for that and more test were added in r310490. We can convert any select-of-constants to math ops: http://rise4fun.com/Alive/d7d For this patch, I'm enhancing an existing x86 transform that uses fake multiplies (they always become shl/lea) to avoid cmov or branching. The current code misses cases where we have a negative constant and a positive constant, so this is just trying to plug that hole. The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start with a select in IR, create a select DAG node, convert it into a sext, convert it back into a select, and then lower it to sext machine code. Some notes about the test diffs: 1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR. 2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. We could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on a different reg? That's a post-DAG problem though. 3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if that's a regression, but those would always be nearly equivalent. 4. pr22338.ll and sext-i1.ll - These tests have undef operands, so we don't actually care about these diffs. 5. sbb.ll - This shows a win for what is likely a common case: choose -1 or 0. 6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again. 7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops. Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass. Differential Revision: https://reviews.llvm.org/D35340
  16. [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. Depends on D35833 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084
  17. [mips] Add missing mips-registered-target to mips test.
Revision 310740 by modocache:
[opt-viewer] Use Python 3-compatible iteritems

Summary:
Replace a usage of a Python 2-specific `dict.iteritems()` with the
Python 3-compatible definition provided at the top of the same file.

Test Plan:
Run `opt-viewer.py` using Python 3 and confirm it no longer encounters a
runtime error when calling `dict.iteritems()`.

Reviewers: anemet

Reviewed By: anemet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36623
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/opt-viewer/optrecord.pyllvm.src/tools/opt-viewer/optrecord.py
Revision 310739 by modocache:
[opt-viewer] Use Python 3-compatible `intern()`

Summary:
In Python 2, `intern()` is a builtin function available to all programs.
In Python 3, it was moved into the `sys` module, available as
`sys.intern`. Import it such that, within `optrecord.py`, `intern()` is
available whether run using Python 2 or 3.

Test Plan:
Run `opt-viewer.py` using Python 3, confirm it no longer
encounters a runtime error when `intern()` is called.

Reviewers: anemet

Reviewed By: anemet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36622
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/opt-viewer/optrecord.pyllvm.src/tools/opt-viewer/optrecord.py
Revision 310738 by rampitec:
[AMDGPU] Fix santizer error after last commit

Removed useless assert.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULibCalls.cppllvm.src/lib/Target/AMDGPU/AMDGPULibCalls.cpp
Revision 310737 by davidxl:
Fix typo /NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/IPO/FunctionImport.cppllvm.src/lib/Transforms/IPO/FunctionImport.cpp
Revision 310735 by dsanders:
[globalisel][tablegen] Generate TypeObject table. NFC

Summary:
Generate the type table from the types used by a target rather than hard-coding
the union of types used by all targets.

Depends on D36084

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: rovka

Subscribers: kristof.beyls, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D36085
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/TableGen/GlobalISelEmitter.tdllvm.src/test/TableGen/GlobalISelEmitter.td
The file was modified/llvm/trunk/utils/TableGen/GlobalISelEmitter.cppllvm.src/utils/TableGen/GlobalISelEmitter.cpp
Revision 310734 by George Karpenkov:
Update libFuzzer documentation for -fsanitize=fuzzer-no-link flag

Differential Revision: https://reviews.llvm.org/D36602
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/LibFuzzer.rstllvm.src/docs/LibFuzzer.rst
Revision 310733 by George Karpenkov:
Add -fsanitize=fuzzer-no-link flag to the driver.

The flag will perform instrumentation necessary to the fuzzing,
but will NOT link libLLVMFuzzer.a library.
Necessary when modifying CFLAGS for projects which may produce
executables as well as a fuzzable target.

Differential Revision: https://reviews.llvm.org/D36600
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Basic/Sanitizers.defclang.src/include/clang/Basic/Sanitizers.def
The file was modified/cfe/trunk/lib/Driver/SanitizerArgs.cppclang.src/lib/Driver/SanitizerArgs.cpp
The file was modified/cfe/trunk/lib/Driver/ToolChains/Darwin.cppclang.src/lib/Driver/ToolChains/Darwin.cpp
The file was modified/cfe/trunk/lib/Driver/ToolChains/Linux.cppclang.src/lib/Driver/ToolChains/Linux.cpp
The file was modified/cfe/trunk/test/Driver/fuzzer.cclang.src/test/Driver/fuzzer.c
Revision 310732 by aaronballman:
Enable exceptions for this test case to speculatively fix the build bots.

Hopefully corrects: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/15666
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/test/clang-tidy/hicpp-exception-baseclass.cppclang-tools-extra.src/test/clang-tidy/hicpp-exception-baseclass.cpp
Revision 310731 by rampitec:
[AMDGPU] Ported and adopted AMDLibCalls pass

The pass does simplifications of well known AMD library calls.
If given -amdgpu-prelink option it works in a pre-link mode which
allows to reference new library functions which will be linked in
later.

In addition it also used to process traditional AMD option
-fuse-native which allows to replace some of the functions with
their fast native implementations from the library.

The necessary glue to pass the prelink option and translate
-fuse-native is to be added to the driver.

Differential Revision: https://reviews.llvm.org/D36436
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPU.hllvm.src/lib/Target/AMDGPU/AMDGPU.h
The file was added/llvm/trunk/lib/Target/AMDGPU/AMDGPULibCalls.cppllvm.src/lib/Target/AMDGPU/AMDGPULibCalls.cpp
The file was added/llvm/trunk/lib/Target/AMDGPU/AMDGPULibFunc.cppllvm.src/lib/Target/AMDGPU/AMDGPULibFunc.cpp
The file was added/llvm/trunk/lib/Target/AMDGPU/AMDGPULibFunc.hllvm.src/lib/Target/AMDGPU/AMDGPULibFunc.h
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cppllvm.src/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/CMakeLists.txtllvm.src/lib/Target/AMDGPU/CMakeLists.txt
The file was added/llvm/trunk/test/CodeGen/AMDGPU/simplify-libcalls.llllvm.src/test/CodeGen/AMDGPU/simplify-libcalls.ll
Revision 310729 by dblaikie:
Orc: PR33769: Don't rely on comparisons with default constructed iterators
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/lli/OrcLazyJIT.hllvm.src/tools/lli/OrcLazyJIT.h
Revision 310727 by aaronballman:
Add hicpp-exception-baseclass to the HIC++ module.

This enforces that throwing an exception in C++ requires that exception to inherit from std::exception.

Patch by Jonas Toth.
Change TypePath in RepositoryPath in Workspace
The file was modified/clang-tools-extra/trunk/clang-tidy/hicpp/CMakeLists.txtclang-tools-extra.src/clang-tidy/hicpp/CMakeLists.txt
The file was added/clang-tools-extra/trunk/clang-tidy/hicpp/ExceptionBaseclassCheck.cppclang-tools-extra.src/clang-tidy/hicpp/ExceptionBaseclassCheck.cpp
The file was added/clang-tools-extra/trunk/clang-tidy/hicpp/ExceptionBaseclassCheck.hclang-tools-extra.src/clang-tidy/hicpp/ExceptionBaseclassCheck.h
The file was modified/clang-tools-extra/trunk/clang-tidy/hicpp/HICPPTidyModule.cppclang-tools-extra.src/clang-tidy/hicpp/HICPPTidyModule.cpp
The file was modified/clang-tools-extra/trunk/docs/ReleaseNotes.rstclang-tools-extra.src/docs/ReleaseNotes.rst
The file was added/clang-tools-extra/trunk/docs/clang-tidy/checks/hicpp-exception-baseclass.rstclang-tools-extra.src/docs/clang-tidy/checks/hicpp-exception-baseclass.rst
The file was modified/clang-tools-extra/trunk/docs/clang-tidy/checks/list.rstclang-tools-extra.src/docs/clang-tidy/checks/list.rst
The file was added/clang-tools-extra/trunk/test/clang-tidy/hicpp-exception-baseclass.cppclang-tools-extra.src/test/clang-tidy/hicpp-exception-baseclass.cpp
Revision 310725 by ctopper:
[AVX512] Remove and autoupgrade many of the broadcast intrinsics

Summary:
This autoupgrades most of the broadcast intrinsics. They've been unused in clang for some time.

This leaves the 32x2 intrinsics because they are still used in clang.

Reviewers: RKSimon, zvi, igorb

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36606
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/IntrinsicsX86.tdllvm.src/include/llvm/IR/IntrinsicsX86.td
The file was modified/llvm/trunk/lib/IR/AutoUpgrade.cppllvm.src/lib/IR/AutoUpgrade.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cppllvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.hllvm.src/lib/Target/X86/X86IntrinsicsInfo.h
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.llllvm.src/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.llllvm.src/test/CodeGen/X86/avx512-intrinsics.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics-upgrade.llllvm.src/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.llllvm.src/test/CodeGen/X86/avx512dq-intrinsics.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.llllvm.src/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512dqvl-intrinsics.llllvm.src/test/CodeGen/X86/avx512dqvl-intrinsics.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.llllvm.src/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
The file was modified/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.llllvm.src/test/CodeGen/X86/avx512vl-intrinsics.ll
Revision 310724 by ctopper:
[x86] Enable some support for lowerVectorShuffleWithUndefHalf with AVX-512

Summary:
This teaches 512-bit shuffles to detect unused halfs in order to reduce shuffle size.

We may need to refine the 512-bit exit point. I couldn't remember if we had good cross lane shuffles for 8/16 bit with AVX-512 or not.

I believe this is step towards being able to handle D36454 without a special case.

From here we need to improve our ability to combine extract_subvector with insert_subvector and other extract_subvectors. And we need to support narrowing binary operations where we don't demand all elements. This may be improvements to DAGCombiner::narrowExtractedVectorBinOp(by recognizing an insert_subvector in addition to concat) or we may need a target specific combiner.

Reviewers: RKSimon, zvi, delena, jbhateja

Reviewed By: RKSimon, jbhateja

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36601
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cppllvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/madd.llllvm.src/test/CodeGen/X86/madd.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sad.llllvm.src/test/CodeGen/X86/sad.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v16.llllvm.src/test/CodeGen/X86/vector-shuffle-512-v16.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.llllvm.src/test/CodeGen/X86/vector-shuffle-512-v32.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v64.llllvm.src/test/CodeGen/X86/vector-shuffle-512-v64.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.llllvm.src/test/CodeGen/X86/vector-shuffle-512-v8.ll
Revision 310718 by gbercea:
[OpenMP] Enable previously successful offloading tests.

Create a separate test file to contain all tests for OpenMP
offloading to GPUs.

Make libdevice checking more robust by accounting for
the case in which no libdevice is found.

This changes are in connrection with diff: D29660
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Driver/ToolChains/Cuda.cppclang.src/lib/Driver/ToolChains/Cuda.cpp
The file was modified/cfe/trunk/lib/Driver/ToolChains/Cuda.hclang.src/lib/Driver/ToolChains/Cuda.h
The file was added/cfe/trunk/test/Driver/openmp-offload-gpu.cclang.src/test/Driver/openmp-offload-gpu.c
The file was modified/cfe/trunk/test/Driver/openmp-offload.cclang.src/test/Driver/openmp-offload.c
Revision 310717 by spatel:
[x86] use more shift or LEA for select-of-constants (2nd try)

The previous rev (r310208) failed to account for overflow when subtracting the
constants to see if they're suitable for shift/lea. This version add a check
for that and more test were added in r310490.

We can convert any select-of-constants to math ops:
http://rise4fun.com/Alive/d7d

For this patch, I'm enhancing an existing x86 transform that uses fake multiplies
(they always become shl/lea) to avoid cmov or branching. The current code misses
cases where we have a negative constant and a positive constant, so this is just
trying to plug that hole.

The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start
with a select in IR, create a select DAG node, convert it into a sext, convert it
back into a select, and then lower it to sext machine code.

Some notes about the test diffs:

1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR.
2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. We could avoid the
   push/pop in some cases if we used 'movzbl %al' instead of an xor on a different reg? That's a
   post-DAG problem though.
3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if
   that's a regression, but those would always be nearly equivalent.
4. pr22338.ll and sext-i1.ll - These tests have undef operands, so we don't actually care about these diffs.
5. sbb.ll - This shows a win for what is likely a common case: choose -1 or 0.
6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again.
7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops.

Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass.

Differential Revision: https://reviews.llvm.org/D35340
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cppllvm.src/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cppllvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.llllvm.src/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
The file was modified/llvm/trunk/test/CodeGen/X86/memcmp-optsize.llllvm.src/test/CodeGen/X86/memcmp-optsize.ll
The file was modified/llvm/trunk/test/CodeGen/X86/memcmp.llllvm.src/test/CodeGen/X86/memcmp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/merge-consecutive-stores.llllvm.src/test/CodeGen/X86/merge-consecutive-stores.ll
The file was modified/llvm/trunk/test/CodeGen/X86/mul-constant-result.llllvm.src/test/CodeGen/X86/mul-constant-result.ll
The file was modified/llvm/trunk/test/CodeGen/X86/pr22338.llllvm.src/test/CodeGen/X86/pr22338.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sbb.llllvm.src/test/CodeGen/X86/sbb.ll
The file was modified/llvm/trunk/test/CodeGen/X86/select.llllvm.src/test/CodeGen/X86/select.ll
The file was modified/llvm/trunk/test/CodeGen/X86/select_const.llllvm.src/test/CodeGen/X86/select_const.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sext-i1.llllvm.src/test/CodeGen/X86/sext-i1.ll
Revision 310716 by dsanders:
[globalisel][tablegen] Support zero-instruction emission.

Summary:
Support the case where an operand of a pattern is also the whole of the
result pattern. In this case the original result and all its uses must be
replaced by the operand. However, register class restrictions can require
a COPY. This patch handles both cases by always emitting the copy and
leaving it for the register allocator to optimize.

Depends on D35833

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D36084
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cppllvm.src/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mirllvm.src/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
The file was modified/llvm/trunk/utils/TableGen/GlobalISelEmitter.cppllvm.src/utils/TableGen/GlobalISelEmitter.cpp
Revision 310715 by sdardis:
[mips] Add missing mips-registered-target to mips test.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/test/Driver/mips-abi.cclang.src/test/Driver/mips-abi.c