Started 2 yr 2 mo ago
Took 49 min on green-dragon-09

Success Build #370 (Aug 13, 2017 10:30:58 AM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 310793
  • http://llvm.org/svn/llvm-project/cfe/trunk : 310778
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 310769
  • http://llvm.org/svn/llvm-project/debuginfo-tests/trunk : 303903
  • http://llvm.org/svn/llvm-project/zorg/trunk : 310746
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 310761
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 310783
Changes
  1. [X86][ARM][TargetLowering] Add SrcVT to isExtractSubvectorCheap

    Summary:
    Without the SrcVT its hard to know what is really being asked for. For example if your target has 128, 256, and 512 bit vectors. Maybe extracting 128 from 256 is cheap, but maybe extracting 128 from 512 is not.

    For x86 we do support extracting a quarter of a 512-bit register. But for i1 vectors we don't have isel patterns for extracting arbitrary pieces. So we need this to have a correct implementation of isExtractSubvectorCheap for mask vectors.

    Reviewers: RKSimon, zvi, efriedma

    Reviewed By: RKSimon

    Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits

    Differential Revision: https://reviews.llvm.org/D36649 (detail)
    by ctopper

Started by timer

This run spent:

  • 20 min waiting;
  • 49 min build duration;
  • 1 hr 9 min total from scheduled to completion.
Test Result (no failures)