FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [clang][CodeGen] Make use of cc1 instead of clang in the tests (details)
  2. [lldb][NFC] Test going up/down one line in the multiline expression (details)
  3. [OpenCL] Fix mangling of single-overload builtins (details)
  4. [CodeGen] Move ARMCodegenPrepare to TypePromotion (details)
  5. [lldb] Remove all remaining tabs from TestReturnValue.py (details)
  6. Fix for buildbots (details)
  7. [lldb][NFC] Extract searching for function SymbolContexts out of (details)
  8. gn build: Merge bc76dadb3cf (details)
  9. [AArch64][SVE] Implement shift intrinsics (details)
  10. Fix compatibility with python3 of clang-include-fixer.py (details)
  11. [VPlan] Add dump function to VPlan class. (details)
  12. Revert "[LiveDebugValues] Introduce entry values of unmodified params" (details)
  13. [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets (details)
  14. [lldb][NFC] Move Curses interface implementation to own file (details)
  15. [Support] Add ProcName to TimeTraceProfiler (details)
  16. Add FunctionDecl::getParameterSourceRange() (details)
  17. [AArch64][SVE2] Implement remaining SVE2 floating-point intrinsics (details)
  18. [NFCI][DebugInfo] Corrected a comment. (details)
  19. [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets (details)
Commit 01a26fa74a9b3ab876a7d3bf30d9aca2d5dfcc7d by kadircet
[clang][CodeGen] Make use of cc1 instead of clang in the tests
The file was modifiedclang/test/CodeGen/arm-neon-vcadd.c
Commit 4821d2a014e02b14223676c98b2ef5244eb91da8 by Raphael Isemann
[lldb][NFC] Test going up/down one line in the multiline expression
editor
The file was addedlldb/packages/Python/lldbsuite/test/commands/expression/multiline-navigation/TestMultilineNavigation.py
Commit 6713670b17324b81cc457f3a37dbc8c1ee229b88 by sven.vanhaastregt
[OpenCL] Fix mangling of single-overload builtins
Commit 9a8d477a0e0 ("[OpenCL] Add builtin function attribute handling",
2019-11-05) stopped Clang from mangling single-overload builtins, which
is incorrect.
The file was modifiedclang/test/CodeGenOpenCL/fdeclare-opencl-builtins.cl
The file was modifiedclang/lib/Sema/SemaLookup.cpp
Commit bc76dadb3cf16c38564ccb1cc54206279b7c54bc by sam.parker
[CodeGen] Move ARMCodegenPrepare to TypePromotion
Convert ARMCodeGenPrepare into a generic type promotion pass by:
- Removing the insertion of arm specific intrinsics to handle narrow
types as we weren't using this.
- Removing ARMSubtarget references.
- Now query a generic TLI object to know which types should be
promoted and what they should be promoted to.
- Move all codegen tests into Transforms folder and testing using opt
and not llc, which is how they should have been written in the
first place...
The pass searches up from icmp operands in an attempt to safely promote
types so we can avoid generating unnecessary unsigned extends during DAG
ISel.
Differential Revision: https://reviews.llvm.org/D69556
The file was removedllvm/test/CodeGen/ARM/CGP/arm-cgp-switch.ll
The file was removedllvm/test/CodeGen/ARM/CGP/arm-cgp-signed-icmps.ll
The file was addedllvm/test/Transforms/TypePromotion/ARM/lit.local.cfg
The file was removedllvm/test/CodeGen/ARM/CGP/arm-cgp-pointers.ll
The file was modifiedllvm/lib/Target/ARM/CMakeLists.txt
The file was addedllvm/test/Transforms/TypePromotion/ARM/icmps.ll
The file was addedllvm/test/Transforms/TypePromotion/ARM/wrapping.ll
The file was removedllvm/test/CodeGen/ARM/CGP/arm-cgp-phis-ret.ll
The file was addedllvm/test/Transforms/TypePromotion/ARM/clear-structures.ll
The file was modifiedllvm/include/llvm/CodeGen/Passes.h
The file was modifiedllvm/include/llvm/InitializePasses.h
The file was modifiedllvm/tools/opt/opt.cpp
The file was removedllvm/test/CodeGen/ARM/CGP/clear-structures.ll
The file was removedllvm/lib/Target/ARM/ARMCodeGenPrepare.cpp
The file was addedllvm/test/Transforms/TypePromotion/ARM/calls.ll
The file was removedllvm/test/CodeGen/ARM/CGP/arm-cgp-signed.ll
The file was addedllvm/test/Transforms/TypePromotion/ARM/casts.ll
The file was addedllvm/test/Transforms/TypePromotion/ARM/switch.ll
The file was removedllvm/test/CodeGen/ARM/CGP/arm-cgp-icmps.ll
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was addedllvm/test/Transforms/TypePromotion/ARM/signed.ll
The file was addedllvm/lib/CodeGen/TypePromotion.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was removedllvm/test/CodeGen/ARM/CGP/arm-cgp-calls.ll
The file was removedllvm/test/CodeGen/ARM/CGP/arm-cgp-casts.ll
The file was removedllvm/test/CodeGen/ARM/CGP/arm-cgp-overflow.ll
The file was addedllvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
The file was modifiedllvm/lib/CodeGen/CodeGen.cpp
The file was addedllvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was addedllvm/test/Transforms/TypePromotion/ARM/pointers.ll
The file was modifiedllvm/lib/Target/ARM/ARM.h
Commit b37a43d93db8c5afb3b95d803638f0536608779d by Raphael Isemann
[lldb] Remove all remaining tabs from TestReturnValue.py
I assumed this was just a single typo, but it seems we actually have a
whole bunch of tabs in this file which cause Python to complain about
mixing tabs and spaces.
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/return-value/TestReturnValue.py
Commit 26bf2a510f7904236982f5f9e83835f36917871a by sam.parker
Fix for buildbots
Change pass name in pipeline test.
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
Commit 16c0653db1150c849bb25f0547abb64349234394 by Raphael Isemann
[lldb][NFC] Extract searching for function SymbolContexts out of
ClangExpressionDeclMap::LookupFunction
This code was just creating a new SymbolContextList with any found
functions in the front and orders them by how close they are to the
current frame. This refactors this code into its own function to make
this more obvious.
Doesn't do any other changes to the code, so this is NFC.
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.h
Commit 14f767393945857d7a4652e1e7a832d44649b496 by llvmgnsyncbot
gn build: Merge bc76dadb3cf
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Commit 7483eb656fd290346e0ad70e553755fe9155e203 by kerry.mclaughlin
[AArch64][SVE] Implement shift intrinsics
Summary: Adds the following intrinsics:
- asr & asrd
- insr
- lsl & lsr
This patch also adds a new AArch64ISD node (INSR) to represent the
int_aarch64_sve_insr intrinsic.
Reviewers: huntergr, sdesmalen, dancgr, mgudim, rengolin, efriedma
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl,
cameron.mcinally, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70437
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-shifts.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
Commit aa189ed25fbd861b07eb5d5116dfd8e33e2b1991 by benny.kra
Fix compatibility with python3 of clang-include-fixer.py
clang-include-fixer was recently updated to be python3-compatible.
However, an exception handling clause was improperly using the
deprecated `message` property of Exception classes, so the code was not
yet entirely python3-compatible.
Differential Revision: https://reviews.llvm.org/D70902
The file was modifiedclang-tools-extra/clang-include-fixer/tool/clang-include-fixer.py
Commit e9c68422dee9d2883b201580867c2edc4f55d49e by flo
[VPlan] Add dump function to VPlan class.
This adds a dump() function to VPlan, which uses the existing
operator<<.
This method provides a convenient way to dump a VPlan while debugging,
e.g. from lldb.
Reviewers: hsaito, Ayal, gilr, rengolin
Reviewed By: hsaito
Differential Revision: https://reviews.llvm.org/D70920
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
Commit 409350deeaf27ab767018b4c4834cfb82919e338 by djordje.todorovic
Revert "[LiveDebugValues] Introduce entry values of unmodified params"
This reverts commit rG4cfceb910692 due to LLDB test failing.
The file was modifiedllvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
The file was removedllvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/main.cpp
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/TestBasicEntryValuesX86_64.py
The file was removedllvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
The file was removedllvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
The file was removedllvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
The file was modifiedllvm/lib/CodeGen/LiveDebugValues.cpp
Commit 6e51ceba536d88f882737c9c4f9ff0ffb0004bfd by sander.desmalen
[AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets
This patch adds the following intrinsics for gather loads with 64-bit
offsets:
     * @llvm.aarch64.sve.ld1.gather (unscaled offset)
     * @llvm.aarch64.sve.ld1.gather.index (scaled offset)
These intrinsics map 1-1 to the following AArch64 instructions
respectively (examples for half-words):
     * ld1h { z0.d }, p0/z, [x0, z0.d]
     * ld1h { z0.d }, p0/z, [x0, z0.d, lsl #1]
Committing on behalf of Andrzej Warzynski (andwar)
Reviewers: sdesmalen, huntergr, rovka, mgudim, dancgr, rengolin,
efriedma
Reviewed By: efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70542
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit 7caa17caf8e290fb865ac81470da737056ab0ace by Raphael Isemann
[lldb][NFC] Move Curses interface implementation to own file
Summary: The IOHandler class source file is currently around 4600 LOC.
However only 200 of these lines are concerned with the actual IOHandler
class and the rest are the implementations for Editline,
IOHandlerConfirm and the Curses interface. All these large features also
cause that the IOHandler (which is in Core) has a large set of
dependencies on other parts of LLDB.
This patch splits out the code for the curses interface into its own
file. This way the simple IOHandler code is no longer buried in-between
much larger functionalities.
Next up is splitting out the other IOHandlers into their own files and
then move them to more appropriate parts of LLDB.
Reviewers: labath, clayborg, JDevlieghere
Reviewed By: labath
Subscribers: mgorny, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D70946
The file was addedlldb/include/lldb/Core/IOHandlerCursesGUI.h
The file was modifiedlldb/include/lldb/Core/IOHandler.h
The file was addedlldb/source/Core/IOHandlerCursesGUI.cpp
The file was modifiedlldb/source/Core/CMakeLists.txt
The file was modifiedlldb/source/Core/IOHandler.cpp
The file was modifiedlldb/source/Commands/CommandObjectGUI.cpp
Commit aedeab7f85caaa0946152e5d73e37455267019bb by russell.gallop
[Support] Add ProcName to TimeTraceProfiler
This was hard-coded to "clang". This change allows it to to be used on
processes other than clang (such as lld).
This gets reported as clang-10 on Linux and clang.exe on Windows so
adapted test to accommodate this.
Differential Revision: https://reviews.llvm.org/D70950
The file was modifiedclang/test/Driver/check-time-trace.cpp
The file was modifiedllvm/include/llvm/Support/TimeProfiler.h
The file was modifiedllvm/lib/Support/TimeProfiler.cpp
The file was modifiedclang/tools/driver/cc1_main.cpp
Commit cc3c935da24c8ebe4fd92638574462b762d92335 by aaron
Add FunctionDecl::getParameterSourceRange()
This source range covers the list of parameters of the function
declaration, including the ellipsis for a variadic function.
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/include/clang/AST/Decl.h
The file was modifiedclang/lib/AST/Decl.cpp
The file was modifiedclang/unittests/AST/SourceLocationTest.cpp
The file was modifiedclang/include/clang/AST/Type.h
The file was modifiedclang/lib/AST/Type.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
Commit 8881ac9c3986bad3a3b96a01fe9d603a740b2107 by kerry.mclaughlin
[AArch64][SVE2] Implement remaining SVE2 floating-point intrinsics
Summary: Adds the following intrinsics:
- faddp
- fmaxp, fminp, fmaxnmp & fminnmp
- fmlalb, fmlalt, fmlslb & fmlslt
- flogb
Reviewers: huntergr, sdesmalen, dancgr, efriedma
Reviewed By: sdesmalen
Subscribers: efriedma, tschuett, kristof.beyls, hiraditya,
cameron.mcinally, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70253
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was addedllvm/test/CodeGen/AArch64/sve2-intrinsics-fp-widening-mul-acc.ll
The file was addedllvm/test/CodeGen/AArch64/sve2-intrinsics-non-widening-pairwise-arith.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm.ll
Commit 8dd17a13b04f00c41bc72fdb12a552f2df26e516 by SourabhSingh.Tomar
[NFCI][DebugInfo] Corrected a comment.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Commit 8bf31e28d7b6eb5743bda82fc5f8a98152b50e57 by sander.desmalen
[Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets
This patch adds intrinsics for SVE gather loads for which the offsets
are 32-bits wide and are:
* unscaled
* @llvm.aarch64.sve.ld1.gather.sxtw
* @llvm.aarch64.sve.ld1.gather.uxtw
* scaled (offsets become indices)
* @llvm.arch64.sve.ld1.gather.sxtw.index
* @llvm.arch64.sve.ld1.gather.uxtw.index The offsets are either zero
(uxtw) or sign (sxtw) extended to 64 bits.
These intrinsics map 1-1 to the corresponding SVE instructions (examples
for half-words):
* unscaled
* ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
* ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
* scaled
* ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]
* ld1h { z0.s }, p0/z, [x0, z0.s, uxtw #1]
Committed on behalf of Andrzej Warzynski (andwar)
Reviewers: sdesmalen, kmclaughlin, eli.friedman, rengolin, rovka,
huntergr, dancgr, mgudim, efriedma
Reviewed By: sdesmalen
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70782
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-scaled-offsets.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td