FailedChanges

Summary

  1. [Codegen] Adjust saturation test. NFC. Add some extra sat tests and adjust some of the existing tests to use signext where it would naturally be.
  2. [Remarks] Add support for prepending a path to external files This helps with testing and debugging for paths that are assumed absolute. It also uses a FileError to provide the file path it's trying to open.
  3. bpf: fix wrong truncation elimination when there is back-edge/loop Currently, BPF backend is doing truncation elimination. If one truncation is performed on a value defined by narrow loads, then it could be redundant given BPF loads zero extend the destination register implicitly. When the definition of the truncated value is a merging value (PHI node) that could come from different code paths, then checks need to be done on all possible code paths. Above described optimization was introduced as r306685, however it doesn't work when there is back-edge, for example when loop is used inside BPF code. For example for the following code, a zero-extended value should be stored into b[i], but the "and reg, 0xffff" is wrongly eliminated which then generates corrupted data. void cal1(unsigned short *a, unsigned long *b, unsigned int k) { unsigned short e; e = *a; for (unsigned int i = 0; i < k; i++) { b[i] = e; e = ~e; } } The reason is r306685 was trying to do the PHI node checks inside isel DAG2DAG phase, and the checks are done on MachineInstr. This is actually wrong, because MachineInstr is being built during isel phase and the associated information is not completed yet. A quick search shows none target other than BPF is access MachineInstr info during isel phase. For an PHI node, when you reached it during isel phase, it may have all predecessors linked, but not successors. It seems successors are linked to PHI node only when doing SelectionDAGISel::FinishBasicBlock and this happens later than PreprocessISelDAG hook. Previously, BPF program doesn't allow loop, there is probably the reason why this bug was not exposed. This patch therefore fixes the bug by the following approach: - The existing truncation elimination code and the associated "load_to_vreg_" records are removed. - Instead, implement truncation elimination using MachineSSA pass, this is where all information are built, and keep the pass together with other similar peephole optimizations inside BPFMIPeephole.cpp. Redundant move elimination logic is updated accordingly. - Unit testcase included + no compilation errors for kernel BPF selftest. Patch Review === Patch was sent to and reviewed by BPF community at: https://lore.kernel.org/bpf Reported-by: David Beckett <david.beckett@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
  4. [RISCV] Add MachineInstr immediate verification Summary: This patch implements the `TargetInstrInfo::verifyInstruction` hook for RISC-V. Currently the hook verifies the machine instruction's immediate operands, to check if the immediates are within the expected bounds. Without the hook invalid immediates are not detected except when doing assembly parsing, so they are silently emitted (including being truncated when emitting object code). The bounds information is specified in tablegen by using the `OperandType` definition, which sets the `MCOperandInfo`'s `OperandType` field. Several RISC-V-specific immediate operand types were created, which extend the `MCInstrDesc`'s `OperandType` `enum`. To have the hook called with `llc` pass it the `-verify-machineinstrs` option. For Clang add the cmake build config `-DLLVM_ENABLE_EXPENSIVE_CHECKS=True`, or temporarily patch `TargetPassConfig::addVerifyPass`. Review concerns: - The patch adds immediate operand type checks that cover at least the base ISA. There are several other operand types for the C extension and one type for the F/D extensions that were left out of this initial patch because they introduced further design concerns that I felt were best evaluated separately. - Invalid register classes (e.g. passing a GPR register where a GPRC is expected) are already caught, so were not included. - This design makes the more abstract `MachineInstr` verification depend on MC layer definitions, which arguably is not the cleanest design, but is in line with how things are done in other parts of the target and LLVM in general. - There is some duplication of logic already present in the `MCOperandPredicate`s. Since the `MachineInstr` and `MCInstr` notions of immediates are fundamentally different, this is currently necessary. Reviewers: asb, lenary Reviewed By: lenary Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67397
  5. [AMDGPU] Fix-up cases where writelane has 2 SGPR operands Summary: Even though writelane doesn't have the same constraints as other valu instructions it still can't violate the >1 SGPR operand constraint Due to later register propagation (e.g. fixing up vgpr operands via readfirstlane) changing writelane to only have a single SGPR is tricky. This implementation puts a new check after SIFixSGPRCopies that prevents multiple SGPRs being used in any writelane instructions. The algorithm used is to check for trivial copy prop of suitable constants into one of the SGPR operands and perform that if possible. If this isn't possible put an explicit copy of Src1 SGPR into M0 and use that instead (this is allowable for writelane as the constraint is for SGPR read-port and not constant-bus access). Reviewers: rampitec, tpr, arsenm, nhaehnle Reviewed By: rampitec, arsenm, nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, mgorny, yaxunl, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D51932 Change-Id: Ic7553fa57440f208d4dbc4794fc24345d7e0e9ea
  6. [libTooling] Fix r374962: add more Transformer forwarding decls. Summary: The move to a new, single namespace in r374962 left out some type definitions from the old namespace and resulted in one naming conflict (`text`). This revision adds aliases for those definitions and removes one of the `text` functions from the new namespace. Reviewers: alexfh Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D69036
  7. [llvm-ar] Make paths case insensitive when on windows When on windows gnu-ar treats member names as case insensitive. This commit implements the same behaviour. Differential Revision: https://reviews.llvm.org/D68033
  8. [Driver,ARM] Make -mfloat-abi=soft turn off MVE. Since `-mfloat-abi=soft` is taken to mean turning off all uses of the FP registers, it should turn off the MVE vector instructions as well as NEON and scalar FP. But it wasn't doing so. So the options `-march=armv8.1-m.main+mve.fp+fp.dp -mfloat-abi=soft` would cause the underlying LLVM to //not// support MVE (because it knows the real target feature relationships and turned off MVE when the `fpregs` feature was removed), but the clang layer still thought it //was// supported, and would misleadingly define the feature macro `__ARM_FEATURE_MVE`. The ARM driver code already has a long list of feature names to turn off when `-mfloat-abi=soft` is selected. The fix is to add the missing entries `mve` and `mve.fp` to that list. Reviewers: dmgreen Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D69025
  9. [Alignment][NFC] Optimize alignTo Summary: A small optimization suggested by jakehehrlich@ in D64790. Reviewers: jakehehrlich, courbet Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69023
  10. RedirectingFileSystem::openFileForRead - replace bitwise & with boolean && to fix warning Seems to be just a typo - now matches other instances which do something similar
  11. RealFile - fix self-initialization warning in constructor.
  12. [InstCombine][AMDGPU] Fix crash with v3i16/v3f16 buffer intrinsics Summary: This is something of a workaround to avoid a crash later on in type legalizer (WidenVectorResult()). Also added some f16 tests, including a non-working v3f16 case with a FIXME. Reviewers: arsenm, tpr, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68865
Revision 375009 by dmgreen:
[Codegen] Adjust saturation test. NFC.

Add some extra sat tests and adjust some of the existing tests to use signext where it would naturally be.
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/CodeGen/AArch64/sadd_sat_plus.llllvm.src/test/CodeGen/AArch64/sadd_sat_plus.ll
The file was added/llvm/trunk/test/CodeGen/AArch64/ssub_sat_plus.llllvm.src/test/CodeGen/AArch64/ssub_sat_plus.ll
The file was added/llvm/trunk/test/CodeGen/AArch64/uadd_sat_plus.llllvm.src/test/CodeGen/AArch64/uadd_sat_plus.ll
The file was added/llvm/trunk/test/CodeGen/AArch64/usub_sat_plus.llllvm.src/test/CodeGen/AArch64/usub_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/sadd_sat.llllvm.src/test/CodeGen/ARM/sadd_sat.ll
The file was added/llvm/trunk/test/CodeGen/ARM/sadd_sat_plus.llllvm.src/test/CodeGen/ARM/sadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/ssub_sat.llllvm.src/test/CodeGen/ARM/ssub_sat.ll
The file was added/llvm/trunk/test/CodeGen/ARM/ssub_sat_plus.llllvm.src/test/CodeGen/ARM/ssub_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/uadd_sat.llllvm.src/test/CodeGen/ARM/uadd_sat.ll
The file was added/llvm/trunk/test/CodeGen/ARM/uadd_sat_plus.llllvm.src/test/CodeGen/ARM/uadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/usub_sat.llllvm.src/test/CodeGen/ARM/usub_sat.ll
The file was added/llvm/trunk/test/CodeGen/ARM/usub_sat_plus.llllvm.src/test/CodeGen/ARM/usub_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sadd_sat.llllvm.src/test/CodeGen/X86/sadd_sat.ll
The file was added/llvm/trunk/test/CodeGen/X86/sadd_sat_plus.llllvm.src/test/CodeGen/X86/sadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/ssub_sat.llllvm.src/test/CodeGen/X86/ssub_sat.ll
The file was added/llvm/trunk/test/CodeGen/X86/ssub_sat_plus.llllvm.src/test/CodeGen/X86/ssub_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/uadd_sat.llllvm.src/test/CodeGen/X86/uadd_sat.ll
The file was added/llvm/trunk/test/CodeGen/X86/uadd_sat_plus.llllvm.src/test/CodeGen/X86/uadd_sat_plus.ll
The file was modified/llvm/trunk/test/CodeGen/X86/usub_sat.llllvm.src/test/CodeGen/X86/usub_sat.ll
The file was added/llvm/trunk/test/CodeGen/X86/usub_sat_plus.llllvm.src/test/CodeGen/X86/usub_sat_plus.ll
Revision 375008 by thegameg:
[Remarks] Add support for prepending a path to external files

This helps with testing and debugging for paths that are assumed
absolute.

It also uses a FileError to provide the file path it's trying to open.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Remarks/RemarkParser.hllvm.src/include/llvm/Remarks/RemarkParser.h
The file was modified/llvm/trunk/lib/Remarks/BitstreamRemarkParser.cppllvm.src/lib/Remarks/BitstreamRemarkParser.cpp
The file was modified/llvm/trunk/lib/Remarks/BitstreamRemarkParser.hllvm.src/lib/Remarks/BitstreamRemarkParser.h
The file was modified/llvm/trunk/lib/Remarks/RemarkParser.cppllvm.src/lib/Remarks/RemarkParser.cpp
The file was modified/llvm/trunk/lib/Remarks/YAMLRemarkParser.cppllvm.src/lib/Remarks/YAMLRemarkParser.cpp
The file was modified/llvm/trunk/lib/Remarks/YAMLRemarkParser.hllvm.src/lib/Remarks/YAMLRemarkParser.h
The file was modified/llvm/trunk/unittests/Remarks/YAMLRemarksParsingTest.cppllvm.src/unittests/Remarks/YAMLRemarksParsingTest.cpp
Revision 375007 by jiwang:
bpf: fix wrong truncation elimination when there is back-edge/loop

Currently, BPF backend is doing truncation elimination. If one truncation
is performed on a value defined by narrow loads, then it could be redundant
given BPF loads zero extend the destination register implicitly.

When the definition of the truncated value is a merging value (PHI node)
that could come from different code paths, then checks need to be done on
all possible code paths.

Above described optimization was introduced as r306685, however it doesn't
work when there is back-edge, for example when loop is used inside BPF
code.

For example for the following code, a zero-extended value should be stored
into b[i], but the "and reg, 0xffff" is wrongly eliminated which then
generates corrupted data.

void cal1(unsigned short *a, unsigned long *b, unsigned int k)
{
  unsigned short e;

  e = *a;
  for (unsigned int i = 0; i < k; i++) {
    b[i] = e;
    e = ~e;
  }
}

The reason is r306685 was trying to do the PHI node checks inside isel
DAG2DAG phase, and the checks are done on MachineInstr. This is actually
wrong, because MachineInstr is being built during isel phase and the
associated information is not completed yet. A quick search shows none
target other than BPF is access MachineInstr info during isel phase.

For an PHI node, when you reached it during isel phase, it may have all
predecessors linked, but not successors. It seems successors are linked to
PHI node only when doing SelectionDAGISel::FinishBasicBlock and this
happens later than PreprocessISelDAG hook.

Previously, BPF program doesn't allow loop, there is probably the reason
why this bug was not exposed.

This patch therefore fixes the bug by the following approach:
- The existing truncation elimination code and the associated
   "load_to_vreg_" records are removed.
- Instead, implement truncation elimination using MachineSSA pass, this
   is where all information are built, and keep the pass together with other
   similar peephole optimizations inside BPFMIPeephole.cpp. Redundant move
   elimination logic is updated accordingly.
- Unit testcase included + no compilation errors for kernel BPF selftest.

Patch Review
===
Patch was sent to and reviewed by BPF community at:

  https://lore.kernel.org/bpf

Reported-by: David Beckett <david.beckett@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/BPF/BPF.hllvm.src/lib/Target/BPF/BPF.h
The file was modified/llvm/trunk/lib/Target/BPF/BPFISelDAGToDAG.cppllvm.src/lib/Target/BPF/BPFISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/BPF/BPFMIPeephole.cppllvm.src/lib/Target/BPF/BPFMIPeephole.cpp
The file was modified/llvm/trunk/lib/Target/BPF/BPFTargetMachine.cppllvm.src/lib/Target/BPF/BPFTargetMachine.cpp
The file was added/llvm/trunk/test/CodeGen/BPF/remove_truncate_6.llllvm.src/test/CodeGen/BPF/remove_truncate_6.ll
Revision 375006 by luismarques:
[RISCV] Add MachineInstr immediate verification

Summary:
This patch implements the `TargetInstrInfo::verifyInstruction` hook for RISC-V. Currently the hook verifies the machine instruction's immediate operands, to check if the immediates are within the expected bounds. Without the hook invalid immediates are not detected except when doing assembly parsing, so they are silently emitted (including being truncated when emitting object code).

The bounds information is specified in tablegen by using the `OperandType` definition, which sets the `MCOperandInfo`'s `OperandType` field. Several RISC-V-specific immediate operand types were created, which extend the `MCInstrDesc`'s `OperandType` `enum`.

To have the hook called with `llc` pass it the `-verify-machineinstrs` option. For Clang add the cmake build config `-DLLVM_ENABLE_EXPENSIVE_CHECKS=True`, or temporarily patch `TargetPassConfig::addVerifyPass`.

Review concerns:

- The patch adds immediate operand type checks that cover at least the base ISA. There are several other operand types for the C extension and one type for the F/D extensions that were left out of this initial patch because they introduced further design concerns that I felt were best evaluated separately.

- Invalid register classes (e.g. passing a GPR register where a GPRC is expected) are already caught, so were not included.

- This design makes the more abstract `MachineInstr` verification depend on MC layer definitions, which arguably is not the cleanest design, but is in line with how things are done in other parts of the target and LLVM in general.

- There is some duplication of logic already present in the `MCOperandPredicate`s. Since the `MachineInstr` and `MCInstr` notions of immediates are fundamentally different, this is currently necessary.

Reviewers: asb, lenary

Reviewed By: lenary

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67397
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cppllvm.src/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cppllvm.src/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.hllvm.src/lib/Target/RISCV/RISCVInstrInfo.h
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.tdllvm.src/lib/Target/RISCV/RISCVInstrInfo.td
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVSubtarget.cppllvm.src/lib/Target/RISCV/RISCVSubtarget.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/Utils/RISCVBaseInfo.hllvm.src/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was added/llvm/trunk/test/CodeGen/RISCV/verify-instr.mirllvm.src/test/CodeGen/RISCV/verify-instr.mir
Revision 375004 by dstuttard:
[AMDGPU] Fix-up cases where writelane has 2 SGPR operands

Summary:
Even though writelane doesn't have the same constraints as other valu
instructions it still can't violate the >1 SGPR operand constraint

Due to later register propagation (e.g. fixing up vgpr operands via
readfirstlane) changing writelane to only have a single SGPR is tricky.

This implementation puts a new check after SIFixSGPRCopies that prevents
multiple SGPRs being used in any writelane instructions.

The algorithm used is to check for trivial copy prop of suitable constants into
one of the SGPR operands and perform that if possible. If this isn't possible
put an explicit copy of Src1 SGPR into M0 and use that instead (this is
allowable for writelane as the constraint is for SGPR read-port and not
constant-bus access).

Reviewers: rampitec, tpr, arsenm, nhaehnle

Reviewed By: rampitec, arsenm, nhaehnle

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, mgorny, yaxunl, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D51932

Change-Id: Ic7553fa57440f208d4dbc4794fc24345d7e0e9ea
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cppllvm.src/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cppllvm.src/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/inserted-wait-states.mirllvm.src/test/CodeGen/AMDGPU/inserted-wait-states.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.llllvm.src/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
Revision 375003 by ymandel:
[libTooling] Fix r374962: add more Transformer forwarding decls.

Summary:
The move to a new, single namespace in r374962 left out some type definitions
from the old namespace and resulted in one naming conflict (`text`).  This
revision adds aliases for those definitions and removes one of the `text`
functions from the new namespace.

Reviewers: alexfh

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D69036
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/Tooling/Transformer/RangeSelector.hclang.src/include/clang/Tooling/Transformer/RangeSelector.h
The file was modified/cfe/trunk/include/clang/Tooling/Transformer/RewriteRule.hclang.src/include/clang/Tooling/Transformer/RewriteRule.h
The file was modified/cfe/trunk/include/clang/Tooling/Transformer/Stencil.hclang.src/include/clang/Tooling/Transformer/Stencil.h
The file was modified/cfe/trunk/unittests/Tooling/TransformerTest.cppclang.src/unittests/Tooling/TransformerTest.cpp
Revision 375002 by gbreynoo:
[llvm-ar] Make paths case insensitive when on windows

When on windows gnu-ar treats member names as case insensitive. This
commit implements the same behaviour.

Differential Revision: https://reviews.llvm.org/D68033
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/CommandGuide/llvm-ar.rstllvm.src/docs/CommandGuide/llvm-ar.rst
The file was added/llvm/trunk/test/tools/llvm-ar/Inputs/path-names.allvm.src/test/tools/llvm-ar/Inputs/path-names.a
The file was added/llvm/trunk/test/tools/llvm-ar/non-windows-name-case.testllvm.src/test/tools/llvm-ar/non-windows-name-case.test
The file was added/llvm/trunk/test/tools/llvm-ar/path-names.testllvm.src/test/tools/llvm-ar/path-names.test
The file was added/llvm/trunk/test/tools/llvm-ar/windows-name-case.testllvm.src/test/tools/llvm-ar/windows-name-case.test
The file was modified/llvm/trunk/tools/llvm-ar/llvm-ar.cppllvm.src/tools/llvm-ar/llvm-ar.cpp
Revision 375001 by statham:
[Driver,ARM] Make -mfloat-abi=soft turn off MVE.

Since `-mfloat-abi=soft` is taken to mean turning off all uses of the
FP registers, it should turn off the MVE vector instructions as well
as NEON and scalar FP. But it wasn't doing so.

So the options `-march=armv8.1-m.main+mve.fp+fp.dp -mfloat-abi=soft`
would cause the underlying LLVM to //not// support MVE (because it
knows the real target feature relationships and turned off MVE when
the `fpregs` feature was removed), but the clang layer still thought
it //was// supported, and would misleadingly define the feature macro
`__ARM_FEATURE_MVE`.

The ARM driver code already has a long list of feature names to turn
off when `-mfloat-abi=soft` is selected. The fix is to add the missing
entries `mve` and `mve.fp` to that list.

Reviewers: dmgreen

Subscribers: kristof.beyls, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D69025
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cppclang.src/lib/Driver/ToolChains/Arch/ARM.cpp
The file was modified/cfe/trunk/test/Driver/arm-mfpu.cclang.src/test/Driver/arm-mfpu.c
Revision 375000 by gchatelet:
[Alignment][NFC] Optimize alignTo

Summary: A small optimization suggested by jakehehrlich@ in D64790.

Reviewers: jakehehrlich, courbet

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69023
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Support/Alignment.hllvm.src/include/llvm/Support/Alignment.h
Revision 374995 by rksimon:
RedirectingFileSystem::openFileForRead - replace bitwise & with boolean && to fix warning

Seems to be just a typo - now matches other instances which do something similar
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Support/VirtualFileSystem.cppllvm.src/lib/Support/VirtualFileSystem.cpp
Revision 374994 by rksimon:
RealFile - fix self-initialization warning in constructor.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Support/VirtualFileSystem.cppllvm.src/lib/Support/VirtualFileSystem.cpp
Revision 374993 by Piotr Sobczak:
[InstCombine][AMDGPU] Fix crash with v3i16/v3f16 buffer intrinsics

Summary:
This is something of a workaround to avoid a crash later on in type
legalizer (WidenVectorResult()).
Also added some f16 tests, including a non-working v3f16 case with
a FIXME.

Reviewers: arsenm, tpr, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68865
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cppllvm.src/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.llllvm.src/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll