SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [LV] Apply sink-after & interleave-groups as VPlan transformations (NFC) (details)
  2. [SystemZ]  Improve handling of huge PC relative immediate offsets. (details)
  3. [lldb][NFC] Remove unused ExpressionParser::Parse (details)
  4. [lldb][NFC] Remove Ocaml from TypeSystem::LLVMCastKind (details)
  5. [hwasan] Remove lazy thread-initialisation (details)
  6. [RISCV] Implement the TargetLowering::getRegisterByName hook (details)
  7. [FIX] Removed duplicated v4f16 and v8f16 declarations (details)
  8. [X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle (details)
  9. [llvm-readobj] Change errors to warnings for symbol section name dumping (details)
  10. [InstSimplify] add more tests for fcmp+select; NFC (details)
  11. [SystemZ] Add GHC calling convention (details)
  12. [OpenCL] Fix address space for const method call from nonconst (PR43145) (details)
  13. [InstSimplify] add more tests for fcmp+select; NFC (details)
  14. [InstSimplify] use FMF to improve fcmp+select fold (details)
  15. [ARM] Add vrev32 NEON fp16 patterns (details)
  16. [ARM] More MVE shuffle tests for sequences that can be converted to (details)
  17. Revert "[LV] Apply sink-after & interleave-groups as VPlan (details)
  18. gn build: add deps, see discussion on D69130 (details)
  19. gn build: run "gn format" (details)
  20. gn build: (manually) merge 51b4b17eb (details)
  21. [SystemZ] Fix typo (details)
  22. Fix compilation warning. NFC. (details)
  23. [IR] adjust assert when replacing undef elements in vector constant (details)
  24. [ARM] Use isFMAFasterThanFMulAndFAdd for MVE (details)
  25. [OpenCL] Fix FileCheck pattern (details)
  26. [X86] Regenerate known-signbits-vector.ll tests. (details)
  27. SanitizerMask::bitPosToMask - fix operator precedence warnings. NFCI. (details)
  28. [MachineVerifier]  Improve verification of live-in lists. (details)
  29. [SystemZ]  Use LivePhysRegs instead of isCCLiveOut() in (details)
  30. [test] Use system locale for mri-utf8.test (details)
  31. [Diagnostics] Improve some error messages related to bad use of (details)
  32. AliasSetTracker - fix uninitialized variable warnings. NFCI. (details)
  33. [X86] Convert ShrinkMode to scoped enum class. NFCI. (details)
  34. [SLP]Fix PR43799: Crash on different sizes of GEP indices. (details)
  35. Fix buildbots troubled by b7b170c. (details)
  36. [Sema] Make helper in TreeTransform.h 'inline' instead of 'static'. NFC (details)
  37. [FPEnv][SelectionDAG] Refactor strict FP node construction (details)
  38. ELF: Discard .ARM.exidx sections for empty functions instead of (details)
  39. Recommit "[CodeView] Add option to disable inline line tables." (details)
  40. Lower generic MASSV entries to PowerPC subtarget-specific entries (details)
  41. Fix static analysis warnings in ARM calling convention lowering (details)
  42. gn build: Merge 40d0d4e2335 (details)
  43. MCDwarfFile::DirIndex - fix uninitialized variable warning. NFCI. (details)
  44. createMCObjectStreamer - fix uninitialized variable warning. NFCI. (details)
  45. VirtualFileSystem - fix uninitialized variable warnings. NFCI. (details)
  46. [X86] Fix uninitialized variable warnings. NFCI. (details)
  47. [ms] Fix Microsoft compatibility handling of commas in nested macro (details)
  48. [lit] Better/earlier errors when no tests are executed (details)
  49. [lit] Move measurement of testing time out of Run.execute (details)
  50. [lldb] [Process/NetBSD] Add register info for missing register sets (details)
  51. [DAGCombine][MSP430] use shift amount threshold in DAGCombine (2/2) (details)
  52. [SimplifyCFG] Use a (trivially) dominanting widenable branch to remove (details)
  53. [X86] Add support for -mvzeroupper and -mno-vzeroupper to match gcc (details)
  54. clang/Modules: Bring back optimization lost in 31e14f41a21f (details)
  55. Fix warning: format specifies type 'unsigned long' but the argument has (details)
  56. Remove unused variables, as suggested by @mcgov. (details)
  57. [demangle] NFC: get rid of NodeOrString (details)
  58. [AMDGPU] deduplicate tablegen predicates (details)
Commit 2be17087f8c38934b7fc9208ae6cf4e9b4d44f4b by gil.rapaport
[LV] Apply sink-after & interleave-groups as VPlan transformations (NFC)
The sink-after and interleave-group vectorization decisions were so far
applied to VPlan during initial VPlan construction, which complicates
VPlan construction – also because of their inter-dependence. This patch
refactors buildVPlanWithRecipes() to construct a simpler initial VPlan
and later apply both these vectorization decisions, in order, as
VPlan-to-VPlan transformations.
Differential Revision: https://reviews.llvm.org/D68577
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
Commit 580310ff0c57a62edd0c07aacfa4969809649444 by paulsson
[SystemZ]  Improve handling of huge PC relative immediate offsets.
Demand that an immediate offset to a PC relative address fits in 32
bits, or else load it into a register and perform a separate add.
Verify in the assembler that such immediate offsets fit the bitwidth.
Even though the final address of a Load Address Relative Long may fit in
32 bits even with a >32 bit offset (depending on where the symbol lives
relative to PC), the GNU toolchain demands the offset by itself to be in
range. This patch adapts the same behavior for llvm.
Review: Ulrich Weigand https://reviews.llvm.org/D69749
The file was modifiedllvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
The file was addedllvm/test/CodeGen/SystemZ/la-05.ll
The file was modifiedllvm/test/MC/SystemZ/insn-bad.s
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Commit 25b486ac4f335fc51240888d6cfbc9c3c211536a by Raphael Isemann
[lldb][NFC] Remove unused ExpressionParser::Parse
Summary: This function is only used internally by ClangExpressionParser.
By putting it in the ExpressionParser class all languages that implement
ExpressionParser::Parse have to share the same signature (which forces
us in downstream to add swift-specific arguments to
ExpressionParser::Parse which then propagate to ClangExpressionParser
and so on).
Reviewers: davide
Subscribers: JDevlieghere, lldb-commits
Tags: #upstreaming_lldb_s_downstream_patches, #lldb
Differential Revision: https://reviews.llvm.org/D69710
The file was modifiedlldb/include/lldb/Expression/ExpressionParser.h
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangFunctionCaller.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.h
Commit bc728d584242946ba59d6bea0cf8c749dcf07248 by Raphael Isemann
[lldb][NFC] Remove Ocaml from TypeSystem::LLVMCastKind
Ocaml support was removed.
The file was modifiedlldb/include/lldb/Symbol/TypeSystem.h
Commit 91167e22eca535025f093335acece573bf19c525 by david.spickett
[hwasan] Remove lazy thread-initialisation
This was an experiment made possible by a non-standard feature of the
Android dynamic loader.
It required introducing a flag to tell the compiler which ABI was being
targeted. This flag is no longer needed, since the generated code now
works for both ABI's.
We leave that flag untouched for backwards compatibility. This also
means that if we need to distinguish between targeted ABI's again we can
do that without disturbing any existing workflows.
We leave a comment in the source code and mention in the help text to
explain this for any confused person reading the code in the future.
Patch by Matthew Malcomson
Differential Revision: https://reviews.llvm.org/D69574
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
The file was modifiedcompiler-rt/lib/hwasan/hwasan_linux.cpp
The file was modifiedcompiler-rt/lib/hwasan/hwasan_interceptors.cpp
The file was removedllvm/test/Instrumentation/HWAddressSanitizer/lazy-thread-init.ll
Commit 51b4b17eb7e6ee2312e3230c7e097df501006360 by luismarques
[RISCV] Implement the TargetLowering::getRegisterByName hook
Summary: The hook should work for any RISC-V register. Non-allocatable
registers do not need to be reserved, for the remaining the hook will
only succeed if you pass clang the -ffixed-xX flag. This builds upon
D67185, which currently only allows reserving GPRs.
Reviewers: asb, lenary
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69130
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/get-register-reserve.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was addedllvm/test/CodeGen/RISCV/get-register-invalid.ll
The file was addedllvm/test/CodeGen/RISCV/get-register-noreserve.ll
Commit 3169f0129a682a54cb90996fcb550184af6cdef9 by diogo.sampaio
[FIX] Removed duplicated v4f16 and v8f16 declarations
Reviewers: RKSimon, ostannard
Reviewed By: RKSimon
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69795
The file was modifiedllvm/lib/Target/ARM/ARMCallingConv.td
Commit 31ed36d0447def348af7b1d27daceb57d063382f by llvm-dev
[X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle
using DemandedElts mask (REAPPLIED)
If we don't demand all elements, then attempt to combine to a simpler
shuffle.
At the moment we can only do this if Depth == 0 as
combineX86ShufflesRecursively uses Depth to track whether the shuffle
has really changed or not - we'll need to change this before we can
properly start merging combineX86ShufflesRecursively into
SimplifyDemandedVectorElts (see D66004).
This reapplies rL368307 (reverted at rL369167) after the fix for the
infinite loop reported at PR43024 was applied at
rG3f087e38a2e7b87a5adaaac1c1b61e51220e7ff3
The file was modifiedllvm/test/CodeGen/X86/shrink_vmul.ll
The file was modifiedllvm/test/CodeGen/X86/vec_umulo.ll
The file was modifiedllvm/test/CodeGen/X86/vec_smulo.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
Commit ef85f47595a905475d3e7b8d1441ed69cb226d9c by jh7370
[llvm-readobj] Change errors to warnings for symbol section name dumping
Also only print each such warning once.
LLVM-style output will now print "<?>" for sections it cannot identify,
e.g. because the section index is invalid. GNU output continues to print
the raw index. In both cases where the st_shndx value is SHN_XINDEX and
the index cannot be looked up in the SHT_SYMTAB_SHNDX section (e.g.
because it is missing), the symbol is printed like other symbols with
st_shndx >= SHN_LORESERVE.
Reviewed by: grimar, MaskRay
Differential Revision: https://reviews.llvm.org/D69671
The file was modifiedllvm/test/tools/llvm-readobj/elf-symbol-shndx.test
The file was modifiedllvm/test/tools/yaml2obj/elf-sht-symtab-shndx.yaml
The file was addedllvm/test/tools/llvm-readobj/elf-section-symbols.test
The file was modifiedllvm/test/tools/yaml2obj/dynamic-symbols.yaml
The file was modifiedllvm/test/Object/invalid.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 499c90afe9099ff700ca8c8f44a2cbf94b1dd627 by spatel
[InstSimplify] add more tests for fcmp+select; NFC
The addition of FMF for select allows more folding for these kinds of
patterns.
The file was modifiedllvm/test/Transforms/InstSimplify/fcmp-select.ll
Commit 22f9429149a8faed1f5770aca89e68409ae2cc4f by ulrich.weigand
[SystemZ] Add GHC calling convention
This is a special calling convention to be used by the GHC compiler.
Author: Stefan Schulze Frielinghaus Differential Revision:
https://reviews.llvm.org/D69024
The file was addedllvm/test/CodeGen/SystemZ/ghc-cc-06.ll
The file was addedllvm/test/CodeGen/SystemZ/ghc-cc-07.ll
The file was addedllvm/test/CodeGen/SystemZ/ghc-cc-02.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
The file was addedllvm/test/CodeGen/SystemZ/ghc-cc-04.ll
The file was addedllvm/test/CodeGen/SystemZ/ghc-cc-05.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZCallingConv.h
The file was addedllvm/test/CodeGen/SystemZ/ghc-cc-03.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZCallingConv.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
The file was addedllvm/test/CodeGen/SystemZ/ghc-cc-01.ll
Commit 82888b78d47ed132aee4993e00669ce7cbd963e0 by sven.vanhaastregt
[OpenCL] Fix address space for const method call from nonconst (PR43145)
Patch by Anastasia Stulova and Sven van Haastregt.
Differential Revision: https://reviews.llvm.org/D68781
The file was modifiedclang/test/CodeGenOpenCLCXX/addrspace-of-this.cl
The file was modifiedclang/lib/Sema/SemaOverload.cpp
Commit ad87f244b4228699806e757fedb39f8996c595f9 by spatel
[InstSimplify] add more tests for fcmp+select; NFC
The easy code fix won't catch non-canonical mismatched constant
patterns, so adding extra coverage for those in case we decide that's
important (but seems unlikely).
The file was modifiedllvm/test/Transforms/InstSimplify/fcmp-select.ll
Commit 659bd73d13686948c2b4dbee02df2f82542849dd by spatel
[InstSimplify] use FMF to improve fcmp+select fold
This is part of a series of patches needed to solve PR39535:
https://bugs.llvm.org/show_bug.cgi?id=39535
The file was modifiedllvm/test/Transforms/InstSimplify/fcmp-select.ll
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
Commit 6bae5d16a28662fee78595e827343ce1c575b1de by david.green
[ARM] Add vrev32 NEON fp16 patterns
Fill in the gaps for vrev32.16 f16 patterns, extending the existing i16
patterns.
Differential Revision: https://reviews.llvm.org/D69508
The file was modifiedllvm/test/CodeGen/ARM/vrev.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrNEON.td
Commit 1c616a9266bd829ea8915617ff83244df45a31c8 by david.green
[ARM] More MVE shuffle tests for sequences that can be converted to
VMOVS. NFC.
The file was addedllvm/test/CodeGen/Thumb2/mve-shufflemov.ll
Commit d3ec06d219788801380af1948c7f7ef9d3c6100b by benny.kra
Revert "[LV] Apply sink-after & interleave-groups as VPlan
transformations (NFC)"
This reverts commit 2be17087f8c38934b7fc9208ae6cf4e9b4d44f4b. Fails
ASAN.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
Commit a3915ca9f908177c53073549e1b9b19e172a45ec by nicolasweber
gn build: add deps, see discussion on D69130
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Commit 9cd13deb293a00da797f7a97e31cdade2d115078 by nicolasweber
gn build: run "gn format"
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
Commit 4168a2e9de35f84abb90fecd03f06a8e131c50fc by nicolasweber
gn build: (manually) merge 51b4b17eb
Also reverts r353980 since that duplicated the GenAsmMatcher target for
AArch64. Instead use visiblity.
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AArch64/AsmParser/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/RISCV/AsmParser/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
Commit d4a7855b68d4d53f121209333d5f2796731ab1f5 by ulrich.weigand
[SystemZ] Fix typo
Typo in comment.  NFC.
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.h
Commit d142ec6fef9a053c9fd9edb5a388203cdb121e65 by michael.hliao
Fix compilation warning. NFC.
The file was modifiedclang/lib/Driver/ToolChains/Darwin.cpp
Commit b556ce3992709e1f6302ca1d4c296f57e83cd6a7 by spatel
[IR] adjust assert when replacing undef elements in vector constant
As noted in follow-up to: rGa1e8ad4f2fa7
It's not safe to assume that an element of the constant is always
non-null. It's definitely not an expected case for the current
instcombine user, but that may not hold if this function is eventually
called from arbitrary places.
The file was modifiedllvm/lib/IR/Constants.cpp
Commit 91b0cad8132997060182146b2734065bc807e9fa by david.green
[ARM] Use isFMAFasterThanFMulAndFAdd for MVE
The Arm backend will usually return false for
isFMAFasterThanFMulAndFAdd, where both the fused VFMA.f32 and a
non-fused VMLA.f32 are usually available for scalar code. For MVE we
don't have the non-fused version though. It makes more sense for
isFMAFasterThanFMulAndFAdd to return true, allowing us to simplify some
of the existing ISel patterns.
The tests here are that non of the existing tests failed, and so we are
still selecting VFMA and VFMS. The one test that changed shows we can
now select from fast math flags, as opposed to just relying on the
isFMADLegalForFAddFSub option.
Differential Revision: https://reviews.llvm.org/D69115
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit 6c5827975cf921563315de54ac7c6053d3995f40 by sven.vanhaastregt
[OpenCL] Fix FileCheck pattern
For this test, FileCheck is not run with the CHECK prefix; it seems
COMMON was intended here.
The file was modifiedclang/test/CodeGenOpenCLCXX/addrspace-of-this.cl
Commit 03cde3a7ccd2025baa497cbcf6e825862429f1bd by llvm-dev
[X86] Regenerate known-signbits-vector.ll tests.
Use X86 instead of X32 and add a common CHECK prefix
The file was modifiedllvm/test/CodeGen/X86/known-signbits-vector.ll
Commit a0324e911374441151903ed0d828e0fc1994c167 by llvm-dev
SanitizerMask::bitPosToMask - fix operator precedence warnings. NFCI.
Fix static analyzer operator precedence warnings with suitable
bracketing. Pull out the mask generation code so clang-format doesn't
make such a mess of it.
The file was modifiedclang/include/clang/Basic/Sanitizers.h
Commit b7b170c9b46ab4c0a10ecf1d9d5832e70ca992d5 by paulsson
[MachineVerifier]  Improve verification of live-in lists.
MachineVerifier::visitMachineFunctionAfter() is extended to check the
live-through case for live-in lists. This is only done for registers
without aliases and that are neither allocatable or reserved, such as
the SystemZ::CC register.
The MachineVerifier earlier only catched the case of a live-in use
without an entry in the live-in list (as "using an undefined physical
register").
A comment in LivePhysRegs.h has been added stating a guarantee that
addLiveOuts() can be trusted for a full register both before and after
register allocation.
Review: Quentin Colombet https://reviews.llvm.org/D68267
The file was addedllvm/test/MachineVerifier/live-ins-03.mir
The file was addedllvm/test/MachineVerifier/live-ins-02.mir
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was addedllvm/test/MachineVerifier/live-ins-01.mir
The file was modifiedllvm/include/llvm/CodeGen/LivePhysRegs.h
Commit bf6744dfb244dbd2a4abe635f57e45218292743f by paulsson
[SystemZ]  Use LivePhysRegs instead of isCCLiveOut() in
SystemZElimCompare.cpp
Review: Ulrich Weigand https://reviews.llvm.org/D68267
The file was modifiedllvm/lib/Target/SystemZ/SystemZElimCompare.cpp
Commit 0bab0538d8cc0de242ed2936a4766930cfc934d2 by thomasp
[test] Use system locale for mri-utf8.test
Summary: llvm-ar's mri-utf8.test test relies on the en_US.UTF-8 locale
to be installed for its last RUN line to work. If not installed, the
unicode string gets encoded (interpreted) as ascii which fails since the
most significant byte is non zero. This commit changes the test to only
rely on the system being able to encode the pound sign in its default
encoding (e.g. UTF-16 for Microsoft Windows) by always opening the file
via input/output redirection. This avoids forcing a given locale to be
present and supported. A Byte Order Mark is also added to help
recognizing the encoding of the file and its endianness. Finally the
XFAIL on system-darwin is removed since the test actually passes fine on
Mac OS X and XFAIL was only added because it failed before.
Reviewers: gbreynoo, MaskRay, rupprecht, JamesNagurne, jfb
Subscribers: dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68472
The file was addedllvm/test/tools/llvm-ar/mri-nonascii.test
The file was removedllvm/test/tools/llvm-ar/mri-utf8.test
Commit 55507110b988c27cfb9ff4c2231fa38171692545 by Dávid Bolvanský
[Diagnostics] Improve some error messages related to bad use of
dynamic_cast
The file was modifiedclang/test/SemaTemplate/instantiate-cast.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaCast.cpp
The file was modifiedclang/test/SemaCXX/dynamic-cast.cpp
Commit 1abb2c1a39fb20e12210472fda42a0c942f83be8 by llvm-dev
AliasSetTracker - fix uninitialized variable warnings. NFCI.
The file was modifiedllvm/include/llvm/Analysis/AliasSetTracker.h
Commit 9ad9d1531b96242bedce3e7f101689bc46322fd2 by llvm-dev
[X86] Convert ShrinkMode to scoped enum class. NFCI.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit b80c41cd3c095c8c4fa739130b560b15bda4bbd0 by a.bataev
[SLP]Fix PR43799: Crash on different sizes of GEP indices.
Summary: If the GEP instructions are going to be vectorized, the indices
in those GEP instructions must be of the same type. Otherwise, the
compiler may crash when trying to build the vector constant.
Reviewers: RKSimon, spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69627
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/crash_gep.ll
Commit b14ff0caecbdbb8312e5671047b9b1dff32da1ca by paulsson
Fix buildbots troubled by b7b170c.
Add '# REQUIRES: systemz-registered-target' in the new tests.
The file was modifiedllvm/test/MachineVerifier/live-ins-01.mir
The file was modifiedllvm/test/MachineVerifier/live-ins-02.mir
The file was modifiedllvm/test/MachineVerifier/live-ins-03.mir
Commit 9ba16615fa07c586965b1fa2dc6e88f13fe8031d by ibiryukov
[Sema] Make helper in TreeTransform.h 'inline' instead of 'static'. NFC
Summary: There seems to be no evidence that having internal linkage for
the function was intentional. Since 'static' functions are normally used
only in .cpp files, using 'inline' in the header file is more
appropriate.
Reviewers: Anastasia
Reviewed By: Anastasia
Subscribers: merge_guards_bot, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69242
The file was modifiedclang/lib/Sema/TreeTransform.h
Commit 664f84e246478db82be2871f36fd1a523d9f2731 by ulrich.weigand
[FPEnv][SelectionDAG] Refactor strict FP node construction
Small refactoring in visitConstrainedFPIntrinsic that should make it
easier to create DAG nodes requiring extra arguments.  That is the case
currently only for STRICT_FP_ROUND, but may be the case for additional
nodes (in particular compares) in the future.
Extracted from the patch for D69281.
NFC.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit 2c6fae179e6984c7330ff8a284d7a10ce142eef9 by peter
ELF: Discard .ARM.exidx sections for empty functions instead of
misordering them.
The logic added in r372781 caused ARMExidxSyntheticSection::addSection()
to return false for exidx sections without a link order dep that passed
isValidExidxSectionDep(). This included exidx sections for empty
functions. As a result, such exidx sections would end up treated like
ordinary sections and would end up being laid out before the
ARMExidxSyntheticSection, most likely in the wrong order relative to the
exidx entries in the ARMExidxSyntheticSection, breaking the orderedness
invariant relied upon by unwinders. Fix this by simply discarding such
sections.
Differential Revision: https://reviews.llvm.org/D69744
The file was addedlld/test/ELF/arm-exidx-empty-fn.s
The file was modifiedlld/ELF/SyntheticSections.cpp
Commit ab76cfdd200d35177df2042a1c0c7e86868d01bc by akhuang
Recommit "[CodeView] Add option to disable inline line tables."
This reverts commit 004ed2b0d1b86d424643ffc88fce20ad8bab6804. Original
commit hash 6d03890384517919a3ba7fe4c35535425f278f89
Summary: This adds a clang option to disable inline line tables. When it
is used, the inliner uses the call site as the location of the inlined
function instead of marking it as an inline location with the function
location.
https://reviews.llvm.org/D67723
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
The file was addedclang/test/CodeGen/debug-info-no-inline-line-tables.c
The file was addedllvm/test/Transforms/Inline/no-inline-line-tables.ll
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/lib/Transforms/Utils/InlineFunction.cpp
The file was modifiedllvm/include/llvm/IR/Attributes.td
The file was modifiedclang/include/clang/Driver/Options.td
Commit 40d0d4e2335d14a3a70a565304fd7e92c25f178b by Jinsong Ji
Lower generic MASSV entries to PowerPC subtarget-specific entries
This patch (second of two patches) lowers the generic PowerPC vector
entries to PowerPC subtarget-specific entries. For instance, the PowerPC
generic entry 'cbrtd2_massv' is lowered to
'cbrtd2_P9' or Power9 subtarget.
The first patch enables the vectorizer to recognize the IBM MASS vector
library routines. This patch specifically adds support for recognizing
the '-vector-library=MASSV' option, and defines mappings from IEEE
standard scalar math functions to generic PowerPC MASS vector
counterparts. For instance, the generic PowerPC MASS vector entry for
double-precision
'cbrt' function is '__cbrtd2_massv'
The overall support for MASS vector library is presented as such in two
patches for ease of review.
Patch by pjeeva01 (Jeeva P.) Differential Revision:
https://reviews.llvm.org/D59883
The file was modifiedllvm/lib/Target/PowerPC/PPC.h
The file was addedllvm/test/CodeGen/PowerPC/lower-massv.ll
The file was modifiedllvm/include/llvm/Analysis/VecFuncs.def
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetMachine.cpp
The file was modifiedllvm/lib/Target/PowerPC/CMakeLists.txt
The file was addedllvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp
The file was addedllvm/test/CodeGen/PowerPC/lower-massv-attr.ll
Commit 73c3137a82c96789f4a2b8ec9427d23fa73498d8 by oliver.stannard
Fix static analysis warnings in ARM calling convention lowering
Fixes https://bugs.llvm.org/show_bug.cgi?id=43891
The file was modifiedllvm/lib/Target/ARM/ARMCallingConv.cpp
Commit 667223c3ed609794495ea30aaea6becd330f9459 by llvmgnsyncbot
gn build: Merge 40d0d4e2335
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn
Commit 692b42fbb0530b41d9575c12e13076d160ab12a5 by llvm-dev
MCDwarfFile::DirIndex - fix uninitialized variable warning. NFCI.
The file was modifiedllvm/include/llvm/MC/MCDwarf.h
Commit 67286c87854adaa5d2826069ce685012e41ce05c by llvm-dev
createMCObjectStreamer - fix uninitialized variable warning. NFCI.
The file was modifiedllvm/include/llvm/Support/TargetRegistry.h
Commit e1000f1d674186c095eac2f252d45ff5b9306db7 by llvm-dev
VirtualFileSystem - fix uninitialized variable warnings. NFCI.
The file was modifiedllvm/lib/Support/VirtualFileSystem.cpp
Commit a8653da4320c5e37fccc54d396f2286a0dce7efe by llvm-dev
[X86] Fix uninitialized variable warnings. NFCI.
The file was modifiedllvm/lib/Target/X86/X86RetpolineThunks.cpp
The file was modifiedllvm/lib/Target/X86/X86WinAllocaExpander.cpp
The file was modifiedllvm/lib/Target/X86/X86IndirectBranchTracking.cpp
The file was modifiedllvm/lib/Target/X86/X86WinEHState.cpp
The file was modifiedllvm/lib/Target/X86/X86OptimizeLEAs.cpp
The file was modifiedllvm/lib/Target/X86/X86FixupLEAs.cpp
The file was modifiedllvm/lib/Target/X86/X86FlagsCopyLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86FixupSetCC.cpp
The file was modifiedllvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
The file was modifiedllvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
Commit be6ac471f613427f3b5b3a306fe033e526d59f76 by epastor
[ms] Fix Microsoft compatibility handling of commas in nested macro
expansions.
In Microsoft-compatibility mode, single commas from nested macro
expansions should not be considered as argument separators; we already
emulated this by marking them to be ignored. However, in MSVC's
preprocessor, subsequent expansions DO treat these commas as argument
separators... so we now ignore each comma at most once.
Includes a small unit test that validates we match MSVC's behavior as
shown in https://gcc.godbolt.org/z/y0twaq
Fixes PR43282
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69626
The file was modifiedclang/lib/Lex/PPMacroExpansion.cpp
The file was modifiedclang/test/Preprocessor/microsoft-ext.c
Commit d8f2bff75126c6dde694ad245f9807fa12ad5630 by julian.lettner
[lit] Better/earlier errors when no tests are executed
Fail early, when we discover no tests at all, or filter out all of them.
The file was modifiedllvm/utils/lit/lit/main.py
The file was modifiedllvm/utils/lit/lit/cl_arguments.py
The file was modifiedllvm/utils/lit/lit/run.py
The file was modifiedllvm/utils/lit/tests/selecting.py
Commit bd14bb42f03a227c7a83db942af4680d2fe0a78d by julian.lettner
[lit] Move measurement of testing time out of Run.execute
The file was modifiedllvm/utils/lit/lit/run.py
The file was modifiedllvm/utils/lit/lit/main.py
Commit 6eca4f46912a8318d7a5888506c3f26c20bdc012 by mgorny
[lldb] [Process/NetBSD] Add register info for missing register sets
Add info for all register sets supported in NetBSD, particularly for all
registers 'expected' by LLDB.  This is necessary in order to fix
python_api/lldbutil/iter/TestRegistersIterator.py test that currently
fails due to missing names of register sets (None).
This copies fpreg descriptions from Linux, and combines Linux' AVX and
MPX registers into a single XState group, to fit NetBSD register group
design.  Technically, we do not support MPX registers at the moment but
gdb-remote insists on passing their errors anyway, and if we do not
include it in any group, they end up in a separate anonymous group that
breaks the test.
While at it, swap the enums for XState and DBRegs to match register set
ordering.
This also adds a few consts to the lldb-x86-register-enums.h to provide
more consistency between user registers and debug registers.
Differential Revision: https://reviews.llvm.org/D69667
The file was modifiedlldb/source/Plugins/Process/Utility/lldb-x86-register-enums.h
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.h
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/register/register/register_command/TestRegisters.py
Commit 113181e9bd05353ed562ee7b971bf7f1e58cd5de by spatel
[DAGCombine][MSP430] use shift amount threshold in DAGCombine (2/2)
Continuation of: D69116
Contributes to a fix for PR43559:
https://bugs.llvm.org/show_bug.cgi?id=43559
See also D69099 and D69116
Use the TLI hook in DAGCombine.cpp to guard against creating shift nodes
that are not optimal for a target.
Patch by: @joanlluch (Joan LLuch)
Differential Revision: https://reviews.llvm.org/D69120
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/MSP430/shift-amount-threshold.ll
Commit 6ff439b57f0fc2b1a2193ae37637c531ff652b1c by listmail
[SimplifyCFG] Use a (trivially) dominanting widenable branch to remove
later slow path blocks
This transformation is a variation on the GuardWidening transformation
we have checked in as it's own pass. Instead of focusing on merge (i.e.
hoisting and simplifying) two widenable branches, this transform makes
the observation that simply removing a second slowpath block (by reusing
an existing one) is often a very useful canonicalization. This may lead
to later merging, or may not. This is a useful generalization when the
intermediate block has loads whose dereferenceability is hard to
establish.
As noted in the patch, this can be generalized further, and will be.
Differential Revision: https://reviews.llvm.org/D69689
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was addedllvm/test/Transforms/SimplifyCFG/wc-widen-block.ll
Commit b2b6a54f847f33f821f41e3e82bf3b86e08817a0 by craig.topper
[X86] Add support for -mvzeroupper and -mno-vzeroupper to match gcc
-mvzeroupper will force the vzeroupper insertion pass to run on CPUs
that normally wouldn't. -mno-vzeroupper disables it on CPUs where it
normally runs.
To support this with the default feature handling in clang, we need a
vzeroupper feature flag in X86.td. Since this flag has the opposite
polarity of the fast-partial-ymm-or-zmm-write we used to use to disable
the pass, we now need to add this new flag to every CPU except KNL/KNM
and BTVER2 to keep identical behavior.
Remove -fast-partial-ymm-or-zmm-write which is no longer used.
Differential Revision: https://reviews.llvm.org/D69786
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedllvm/lib/Target/X86/X86.td
The file was modifiedllvm/lib/Target/X86/X86Subtarget.h
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.h
The file was modifiedclang/test/Driver/x86-target-features.c
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedllvm/lib/Target/X86/X86VZeroUpper.cpp
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedllvm/test/CodeGen/X86/avx-vzeroupper.ll
Commit 8112a423a8ede9bce64b6553e6451bf10995105c by Duncan P. N. Exon Smith
clang/Modules: Bring back optimization lost in 31e14f41a21f
31e14f41a21f9016050a20f07d5da03db2e8c13e accidentally dropped caching of
failed module loads.  This brings it back by making
ModuleMap::getCachedModuleLoad return an Optional.
The file was modifiedclang/lib/Frontend/CompilerInstance.cpp
The file was modifiedclang/include/clang/Lex/ModuleMap.h
Commit 9cc3ebf8b7630e30bc0eea6dc4a55348edf71091 by alexandre.ganea
Fix warning: format specifies type 'unsigned long' but the argument has
type 'unsigned long long' [-Wformat]
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_bitvector_test.cpp
Commit efad56b2be9b9f7d5b62d1f06541192fa6b537ee by alexandre.ganea
Remove unused variables, as suggested by @mcgov.
Fixes warning: unused variable 'XXX' [-Wunused-const-variable]
The file was modifiedcompiler-rt/lib/asan/asan_malloc_win.cpp
Commit af11f417fc7d2390da4a883c05c098f23891862e by erik.pilkington
[demangle] NFC: get rid of NodeOrString
This class was a bit overengineered, and was triggering some PVS
warnings. Instead, put strings into a NameType and let clients
unconditionally treat it as a Node.
The file was modifiedlibcxxabi/src/cxa_demangle.cpp
The file was modifiedlibcxxabi/src/demangle/ItaniumDemangle.h
The file was modifiedllvm/lib/Support/ItaniumManglingCanonicalizer.cpp
The file was modifiedllvm/include/llvm/Demangle/ItaniumDemangle.h
The file was modifiedllvm/lib/Demangle/ItaniumDemangle.cpp
Commit 4312c4afd43209400df53ca541b4b19919f797af by Stanislav.Mekhanoshin
[AMDGPU] deduplicate tablegen predicates
We are duplicating predicates if several parts of the combined predicate
list contain the same condition. Added code to deduplicate the list.
We have AssemblerPredicates and AssemblerPredicate in the
PredicateControl, but we never use AssemblerPredicates with an actual
list, so this one is dropped.
This addresses the first part of the llvm bug 43886:
https://bugs.llvm.org/show_bug.cgi?id=43886
Differential Revision: https://reviews.llvm.org/D69815
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOPCInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/MIMGInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SMInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td