FailedChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [X86] Factor constant pool comment printing out of the switch in X86AsmPrinter::emitInstruction. NFC (details)
  2. [X86] Minor cleanups to addShuffleComments in X86MCInstPrinter.cpp. NFCI (details)
  3. Remove some non-determinism from the `Darwin/duplicate_os_log_reports.cpp` test. (details)
  4. [Driver] Fix BooleanFFlag identifiers to use 'f' 'fno_' prefixes instead of suffixes (details)
  5. [X86] Add pseudo instructions to use MULX with a single destination when the low result isn't used. (details)
  6. [llvm-objdump] Simplify reportError() and prepend outs().flush() (details)
  7. [llvm-objdump] Move llvm:: to llvm::objdump:: and qualifying definitions with objdump:: (details)
  8. [llvm-objdump] Delete unneeeded namespace llvm {} (details)
  9. [ELF][docs] Update supported targets (details)
  10. [X86] Move MMX_SET0 pattern into the instruction definition. NFC (details)
  11. [X86] Autogenerate complete checks. NFC (details)
  12. [X86] Fix a place where we created MOVQ2DQ with a DstVT other than v2i64. (details)
  13. [X86] Teach computeKnownBitsForTargetNode that the upper half of X86ISD::MOVQ2DQ is all zero. (details)
  14. [DAGCombiner] Move debug message and statistic update into CommitTargetLoweringOpt. (details)
  15. [X86] Add DAG combine to turn (v2i64 (scalar_to_vector (i64 (bitconvert (mmx))))) to MOVQ2DQ. Remove unneeded isel patterns. (details)
  16. [X86] Remove unneeded bitconverts from isel patterns. NFC (details)
  17. AMDGPU: Add setTruncStoreAction for vector i64 types made legal recently (details)
  18. [AMDGPU] Precommit tests for D80813 (details)
  19. [AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS (details)
  20. [NFC][PowerPC] Add a new case to test phi-node-elimination pass (details)
  21. Revert "[NFC][PowerPC] Add a new case to test phi-node-elimination pass" (details)
  22. [ScheduleDAG] Avoid unnecessary recomputation of topological order. (details)
Commit 3eb430d59847b9e0091199cb63a50ab0494711dd by craig.topper
[X86] Factor constant pool comment printing out of the switch in X86AsmPrinter::emitInstruction. NFC

Pull the verbose asm check out of the cases and move it up to
the call of the new function.
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
Commit 16976cb92535b0620f46720fe3be283da904026c by craig.topper
[X86] Minor cleanups to addShuffleComments in X86MCInstPrinter.cpp. NFCI

-Replace some ifs that should be impossible with asserts.
-Use X86::AddrDisp and X86::AddrNumOperands to make code more readable
-Use X86II::isKMasked/isKMergeMasked to do some operand skipping to remove or simplify switches
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
Commit fc532c1a0dc66bf23cac60f5363f180c6cbfefbc by Dan Liew
Remove some non-determinism from the `Darwin/duplicate_os_log_reports.cpp` test.

The test read from an uninitialized buffer which could cause the output
to be unpredictable.

The test is currently disabled so this won't actually change anything
until the test is re-enabled.
The file was modifiedcompiler-rt/test/asan/TestCases/Darwin/duplicate_os_log_reports.cpp
Commit 1b6d29e06b07e518025b6f06445ad3275d6f5684 by maskray
[Driver] Fix BooleanFFlag identifiers to use 'f' 'fno_' prefixes instead of suffixes
The file was modifiedclang/include/clang/Driver/Options.td
Commit 07e8a780d81bb58a0c7bd4da6cc0b9beaec3c788 by craig.topper
[X86] Add pseudo instructions to use MULX with a single destination when the low result isn't used.

The instruction is defined to only produce high result if both
destinations are the same. We can exploit this to avoid
unnecessarily clobbering a register.

In order to hide this from register allocation we use a pseudo
instruction and expand the result during MCInst creation.

Differential Revision: https://reviews.llvm.org/D80500
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/lib/Target/X86/X86InstrArithmetic.td
The file was modifiedllvm/test/CodeGen/X86/pr35636.ll
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
The file was modifiedllvm/test/CodeGen/X86/i128-mul.ll
Commit a23d1e9aff4d8cb752e227b3e16f887cf49c15d4 by maskray
[llvm-objdump] Simplify reportError() and prepend outs().flush()

As noticed by dblaikie.

I don't know what code paths using reportError can cause stdout output
to be interleaved with stderr, so no test is added now.

Also drop an unneeded use of errs().fflush() in reportWarning().
I requested this in D64165.
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
Commit 439d27d79f58282b618881142244bbdcb1f28345 by maskray
[llvm-objdump] Move llvm:: to llvm::objdump:: and qualifying definitions with objdump::

Or adding `static`.

Qualifying definitions with `objdump::` comforms to the coding standards
https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was modifiedllvm/tools/llvm-objdump/COFFDump.cpp
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.h
Commit d04eb253c710aec30707e404cfc9dc672082d3a2 by maskray
[llvm-objdump] Delete unneeeded namespace llvm {}
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
Commit ce1fadca608ffaf214732b843e084a75e55fcb50 by maskray
[ELF][docs] Update supported targets

PowerPC, PowerPC64 and x86-32 have production quality.
Mention Hexagon, RISC-V and SPARC V9.
The file was modifiedlld/docs/index.rst
Commit 8857822452c758805e8bb33ecc877d8d0cce1660 by craig.topper
[X86] Move MMX_SET0 pattern into the instruction definition. NFC
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
Commit efc5857b0b121ffd0b74fcd7aa8c48419a3fe4fc by craig.topper
[X86] Autogenerate complete checks. NFC
The file was modifiedllvm/test/CodeGen/X86/pr23246.ll
Commit 1ecf39d607acdb04c2bb5155e5f7265db2484511 by craig.topper
[X86] Fix a place where we created MOVQ2DQ with a DstVT other than v2i64.

The type profile and isel pattern have this type declared as
being MVT::v2i64. But isel skips the explicit type check due to
the type profile.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit af1accdd860d4e1768a1f56a8651ae4d13445e14 by craig.topper
[X86] Teach computeKnownBitsForTargetNode that the upper half of X86ISD::MOVQ2DQ is all zero.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_insert-7.ll
The file was modifiedllvm/test/CodeGen/X86/mmx-cvt.ll
Commit a4dd45b7d09d8c12b87eaa0e6d1a92ce2b0defe0 by craig.topper
[DAGCombiner] Move debug message and statistic update into CommitTargetLoweringOpt.

This code was repeated in two callers of CommitTargetLoweringOpt.
But CommitTargetLoweringOpt is also called from TargetLowering.
We should print a message for those calls to. So sink the
repeated code into CommitTargetLoweringOpt to catch those calls.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 7c3b8077cc3feed2de3de6f3efb0627d619d1434 by craig.topper
[X86] Add DAG combine to turn (v2i64 (scalar_to_vector (i64 (bitconvert (mmx))))) to MOVQ2DQ. Remove unneeded isel patterns.

We already had a DAG combine for (mmx (bitconvert (i64 (extractelement v2i64))))
to MOVDQ2Q.

Remove patterns for MMX_MOVQ2DQrr/MMX_MOVDQ2Qrr that use
scalar_to_vector/extractelement involving i64 scalar type with
v2i64 and x86mmx.
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit dbda87186ec1b28a98d7a91a651b5a47c6f06d40 by craig.topper
[X86] Remove unneeded bitconverts from isel patterns. NFC

The types already match so TableGen is removing the bitconvert.
The file was modifiedllvm/lib/Target/X86/X86InstrMMX.td
Commit 234eba90f4f346a4b0d260cdd61a9aae647b2b48 by changpeng.fang
AMDGPU: Add setTruncStoreAction for vector i64 types made legal recently

Reviewers:
  rampitec, arsenm

Differential Revision:
  https://reviews.llvm.org/D80853
The file was addedllvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit d4751f35560321dfb38cd77b924e715b9ebf9203 by jay.foad
[AMDGPU] Precommit tests for D80813
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.sin.ll
Commit 2768edfff19a170faca35a8c63163c8bb1b67382 by jay.foad
[AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS

Differential Revision: https://reviews.llvm.org/D80813
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.sin.ll
Commit af3abbf7bd2213003a133c361c212ac6efb1bd2b by shkzhang
[NFC][PowerPC] Add a new case to test phi-node-elimination pass
The file was addedllvm/test/CodeGen/PowerPC/phi-eliminate.mir
Commit bfdf9ef009ab335981747f09a2c6b9a41c0462b4 by shkzhang
Revert "[NFC][PowerPC] Add a new case to test phi-node-elimination pass"
This case wll be failed on some machines which enable expensive-checks.

This reverts commit af3abbf7bd2213003a133c361c212ac6efb1bd2b.
The file was removedllvm/test/CodeGen/PowerPC/phi-eliminate.mir
Commit ec25a71eb7fc72440149784951d62453301cc960 by flo
[ScheduleDAG] Avoid unnecessary recomputation of topological order.

In some cases ScheduleDAGRRList has to add new nodes to resolve problems
with interfering physical registers. When new nodes are added, it
completely re-computes the topological order, which can take a long
time, but is unnecessary. We only add nodes one by one, and initially
they do not have any predecessors. So we can just insert them at the end
of the vector. Later we add predecessors, but the helper function
properly updates the topological order much more efficiently. With this
change, the compile time for the program below drops from 300s to 30s on
my machine.

    define i11129 @test1() {
      %L1 = load i11129, i11129* undef
      %B30 = ashr i11129 %L1, %L1
      store i11129 %B30, i11129* undef
      ret i11129 %L1
    }

This should be generally beneficial, as we can skip a large amount of
work. Theoretically there are some scenarios where we might not safe
much, e.g. when we add a dependency between the first and last node.
Then we would have to shift all nodes. But we still do not have to spend
the time re-computing the initial order.

Reviewers: MatzeB, atrick, efriedma, niravd, paquette

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D59722
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAG.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
The file was modifiedllvm/lib/CodeGen/ScheduleDAG.cpp