SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. Changed to use cmake arguments to specify C and C++ compilers. (details)
Commit 94e652786cb7bbf750d37816c4f099aa4081f4be by gkistanova
Changed to use cmake arguments to specify C and C++ compilers.
The file was modifiedzorg/buildbot/builders/ClangBuilder.py

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [compiler-rt] [scudo] Fix typo in function attribute (details)
  2. [ARM] Sink splats to MVE intrinsics (details)
  3. [amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel. (details)
  4. [libc++] Remove some workarounds for missing variadic templates (details)
  5. [Coroutine] Fix a bug where Coroutine incorrectly spills phi and invoke defs before CoroBegin (details)
  6. [OpenMP 5.0] Fix user-defined mapper privatization in tasks (details)
  7. [DFSan] Add bcmp wrapper. (details)
  8. Precommit test updates (details)
  9. [AArch64] Match pairwise add/fadd pattern (details)
  10. [CUDA][HIP] Defer overloading resolution diagnostics for host device functions (details)
  11. [ARM] Add more MVE postinc distribution tests. NFC (details)
  12. [mlir][openacc] Change operand type from index to AnyInteger in parallel op (details)
  13. [flang][openacc] Lower clauses on loop construct to OpenACC dialect (details)
  14. [Test] Add tests showing that IndVars cannot prove (X + 1 > X) (details)
  15. Revert "[DFSan] Add bcmp wrapper." (details)
  16. ModuloSchedule.cpp - remove unnecessary includes. NFCI. (details)
  17. Fix build failure in clangd (details)
  18. [mlir][Vector] Add a folder for vector.broadcast (details)
  19. [AArch64][GlobalISel] Fix bug in fewVectorElts action while legalizing oversize G_FPTRUNC vectors. (details)
  20. [ARM] Expand distributing increments to also handle existing pre/post inc instructions. (details)
  21. [InstSimplify] add tests for FP constant miscompile; NFC (PR43907) (details)
  22. [amdgpu] Compilation fix for Release (details)
  23. [SyntaxTree][Synthesis] Fix allocation in `createTree` for more general use (details)
  24. [DFSan] Add bcmp wrapper. (details)
  25. [Sema] Introduce BuiltinAttr, per-declaration builtin-ness (details)
  26. [AMDGPU] Fix ROCm unit test memref initialization (details)
  27. Add missing include (details)
  28. [PowerPC][AIX] Don't hardcode python invoke command line (details)
  29. [VectorCombine] add test for multi-use load (PR47558); NFC (details)
  30. [VectorCombine] rearrange bailouts for load insert for efficiency; NFC (details)
  31. Revert "[CUDA][HIP] Defer overloading resolution diagnostics for host device functions" (details)
  32. Revert "[NFC] Refactor DiagnosticBuilder and PartialDiagnostic" (details)
  33. [MLIR] Support for return values in Affine.For yield (details)
  34. [MLIR][Affine] Add parametric tile size support for affine.for tiling (details)
  35. [X86] Don't match x87 register inline asm constraints unless the VT is floating point or its a clobber (details)
  36. [VectorCombine] limit load+insert transform to one-use (details)
  37. [AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal for shifts. (details)
  38. [AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b. (details)
  39. [PDB] Split TypeServerSource and extend type index map lifetime (details)
  40. [SVE][WIP] Implement lowering for fixed length VSELECT to Scalable (details)
  41. [IRSim] Adding IR Instruction Mapper (details)
  42. [gn build] Port 7e4c6fb8546 (details)
  43. AArch64::ArchKind's underlying type is uint64_t (details)
  44. [Lsan] Use fp registers to search for pointers (details)
  45. Disable hoisting MI to hotter basic blocks when using pgo (details)
  46. [SCEV] Add test cases for max BTC with loop guard info. (details)
  47. [GVN] Add additional assume tests (NFC) (details)
  48. [GVN] Use that assume(!X) implies X==false (PR47496) (details)
  49. [LoopUnrollAndJam] Allow unroll and jam loops forced by user. (details)
  50. [InstCombine] Canonicalize SPF_ABS to abs intrinc (details)
  51. [llvm-install-name-tool] Update the command-line guide (details)
  52. [NewPM] Fix pr45927.ll under NPM (details)
  53. [MemorySSA] Be more conservative when traversing MemoryPhis. (details)
  54. Support dwarf fission for wasm object files (details)
  55. [TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator (details)
  56. [test] Fix FullUnroll.ll (details)
  57. [AArch64] Enable implicit null check transformation (details)
  58. [RISCV] Support Shadow Call Stack (details)
  59. [MLIR][TableGen] Automatic detection and elimination of redundant methods (details)
  60. [MemorySSA] Fix an unused variable warning [NFC] (details)
  61. [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang (details)
  62. [PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests (details)
  63. [AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC. (details)
  64. [AArch64][GlobalISel] Make G_STORE <8 x s8> legal. (details)
  65. [lldb] Clarify docstring for SBBlock::IsInlined, NFC (details)
  66. [mlir][shape] Add `shape.cstr_require %bool` (details)
  67. [MLIR] Fix build failure due to https://reviews.llvm.org/D87059. (details)
  68. [scudo/standalone] Don't define test main function for Fuchsia (details)
  69. [NFC][Lsan] Fix zero-sized array compilation error (details)
  70. [NFC] clang-format one line (details)
Commit 7b2dd58eb09d3ead649bdd0a67f69d8776a636ff by n54
[compiler-rt] [scudo] Fix typo in function attribute

Fixes the build after landing https://reviews.llvm.org/D87562
The file was modifiedcompiler-rt/lib/scudo/scudo_allocator.cpp
Commit 34b27b9441d27ef886ea22b3bb75b357a5ec707b by david.green
[ARM] Sink splats to MVE intrinsics

The predicated MVE intrinsics are generated as, for example,
llvm.arm.mve.add.predicated(x, splat(y). p). We need to sink the splat
value back into the loop, like we do for other instructions, so we can
re-select qr variants.

Differential Revision: https://reviews.llvm.org/D87693
The file was modifiedllvm/test/CodeGen/Thumb2/mve-qrintr.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit c3492a1aa1b98c8d81b0969d52cea7681f0624c2 by michael.hliao
[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel.

- Need to lower COPY from SGPR to VGPR to a real instruction as the
  standard COPY is used where the source and destination are from the
  same register bank so that we potentially coalesc them together and
  save one COPY. Considering that, backend optimizations, such as CSE,
  won't handle them. However, the copy from SGPR to VGPR always needs
  materializing to a native instruction, it should be lowered into a
  real one before other backend optimizations.

Differential Revision: https://reviews.llvm.org/D87556
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-fabs.ll
The file was addedllvm/test/CodeGen/AMDGPU/sgpr-copy-cse.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fabs.ll
Commit a3c28ccd49391931acd8b3b27dc98d7c606051e0 by Louis Dionne
[libc++] Remove some workarounds for missing variadic templates

We don't support GCC in C++03 mode, and Clang provides variadic templates
even in C++03 mode. So there's effectively no supported compiler that
doesn't support variadic templates.

This effectively gets rid of all uses of _LIBCPP_HAS_NO_VARIADICS, but
some workarounds for the lack of variadics remain.
The file was removedlibcxx/test/std/utilities/meta/meta.unary/meta.unary.cat/member_function_pointer_no_variadics.pass.cpp
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/include/future
The file was modifiedlibcxx/include/__config
Commit 5b533d6cdeed21369dee4572b5485b1fd5d5dcf5 by xun
[Coroutine] Fix a bug where Coroutine incorrectly spills phi and invoke defs before CoroBegin

When a spill definition is before CoroBegin, we cannot spill it to the frame immediately after the definition. We have to spill it after the frame is ready.
The current implementation handles it properly for any other kinds of instructions except for PhINode and InvokeInst, which could also be defined before CoroBegin.
This patch fixes it by moving the CoroBegin dominance check earlier, so that it covers all cases.
Added a test.

Differential Revision: https://reviews.llvm.org/D87810
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was addedllvm/test/Transforms/Coroutines/coro-spill-defs-before-corobegin.ll
Commit d5ce8233bfcfdeb66c715a1def8e0b34d236d48a by a.bataev
[OpenMP 5.0] Fix user-defined mapper privatization in tasks

This patch fixes the problem that user-defined mapper array is not correctly privatized inside a task. This problem causes openmp/libomptarget/test/offloading/target_depend_nowait.cpp fails.

Differential Revision: https://reviews.llvm.org/D84470
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
The file was modifiedclang/test/OpenMP/target_depend_codegen.cpp
Commit 559f9198125392bfa8e7d462aa8e87fcf5030185 by mascasa
[DFSan] Add bcmp wrapper.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87801
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt
The file was modifiedcompiler-rt/test/dfsan/custom.cpp
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp
Commit 3ee87a976d52a2379d007046f9a1ad4a07f440c0 by Sanne.Wouda
Precommit test updates
The file was addedllvm/test/CodeGen/AArch64/faddp-half.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fadd.ll
The file was addedllvm/test/CodeGen/AArch64/faddp.ll
Commit d5fd3d9b903ef6d96c6b3b82434dd0461faaba55 by Sanne.Wouda
[AArch64] Match pairwise add/fadd pattern

D75689 turns the faddp pattern into a shuffle with vector add.

Match this new pattern in target-specific DAG combine, rather than ISel,
because legalization (for v2f32) turns it into a bit of a mess.

- extended to cover f16, f32, f64 and i64
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fadd.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/faddp.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/faddp-half.ll
Commit 40df06cdafc010002fc9cfe1dda73d689b7d27a6 by Yaxun.Liu
[CUDA][HIP] Defer overloading resolution diagnostics for host device functions

In CUDA/HIP a function may become implicit host device function by
pragma or constexpr. A host device function is checked in both
host and device compilation. However it may be emitted only
on host or device side, therefore the diagnostics should be
deferred until it is known to be emitted.

Currently clang is only able to defer certain diagnostics. This causes
false alarms and limits the usefulness of host device functions.

This patch lets clang defer all overloading resolution diagnostics for host device functions.

An option -fgpu-defer-diag is added to control this behavior. By default
it is off.

It is NFC for other languages.

Differential Revision: https://reviews.llvm.org/D84364
The file was modifiedclang/include/clang/Basic/DiagnosticDriver.h
The file was modifiedclang/tools/diagtool/DiagnosticNames.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/test/TableGen/DiagnosticBase.inc
The file was addedclang/test/TableGen/deferred-diag.td
The file was addedclang/test/SemaCUDA/deferred-oeverload.cu
The file was modifiedclang/lib/Driver/ToolChains/Cuda.cpp
The file was modifiedclang/lib/Sema/AnalysisBasedWarnings.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaTemplateVariadic.cpp
The file was modifiedclang/utils/TableGen/ClangDiagnosticsEmitter.cpp
The file was modifiedclang/lib/Sema/SemaExprObjC.cpp
The file was modifiedclang/lib/Sema/SemaAttr.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticCrossTU.h
The file was modifiedclang/include/clang/Basic/Diagnostic.td
The file was modifiedclang/lib/Sema/SemaSYCL.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticComment.h
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticAnalysis.h
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/lib/Sema/SemaStmtAsm.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticRefactoring.h
The file was modifiedclang/include/clang/Basic/DiagnosticAST.h
The file was modifiedclang/include/clang/Basic/DiagnosticIDs.h
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticLex.h
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/lib/Basic/DiagnosticIDs.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Sema/SemaCUDA.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSema.h
The file was modifiedclang/include/clang/Basic/DiagnosticParse.h
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was modifiedclang/include/clang/Basic/DiagnosticFrontend.h
The file was modifiedclang/include/clang/Basic/DiagnosticSerialization.h
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
Commit 72a4a478fe12f3052d1f73c5e5b4a905c8dfcf1b by david.green
[ARM] Add more MVE postinc distribution tests. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
Commit 6d3cabd90eedee07a6e6cbf2dfa952e23cef192c by clementval
[mlir][openacc] Change operand type from index to AnyInteger in parallel op

This patch change the type of operands async, wait, numGangs, numWorkers and vectorLength from index
to AnyInteger to fit with acc.loop and the OpenACC specification.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D87712
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Commit f0e028f4b32393676b5d3eb36d6598ec5a390180 by clementval
[flang][openacc] Lower clauses on loop construct to OpenACC dialect

Lower OpenACCLoopConstruct and most of the clauses to the OpenACC acc.loop operation in MLIR.
This patch refelcts what can be upstream from PR flang-compiler/f18-llvm-project#419

Reviewed By: SouraVX

Differential Revision: https://reviews.llvm.org/D87389
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRDialect.h
The file was modifiedflang/lib/Lower/OpenACC.cpp
Commit 7688027f166311164982bb15fe44041f31b6d45f by mkazantsev
[Test] Add tests showing that IndVars cannot prove (X + 1 > X)
The file was addedllvm/test/Transforms/IndVarSimplify/trivial-checks.ll
Commit df017fd906bba81af38749fe374ae2635fd51389 by mascasa
Revert "[DFSan] Add bcmp wrapper."

This reverts commit 559f9198125392bfa8e7d462aa8e87fcf5030185 due to bot
failure.
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp
The file was modifiedcompiler-rt/test/dfsan/custom.cpp
Commit 2a56a0ba086491e51c54026c6badae6496539487 by llvm-dev
ModuloSchedule.cpp - remove unnecessary includes. NFCI.

Already included in ModuloSchedule.h
The file was modifiedllvm/lib/CodeGen/ModuloSchedule.cpp
Commit 7f1f89ec8d9944559042bb6d3b1132eabe3409de by Yaxun.Liu
Fix build failure in clangd
The file was modifiedclang-tools-extra/clangd/Diagnostics.cpp
Commit f16abe5f84eee8db18d5eb5a21ab543146626ea6 by hanchung
[mlir][Vector] Add a folder for vector.broadcast

Fold the operation if the source is a scalar constant or splat constant.

Update transform-patterns-matmul-to-vector.mlir because the broadcast ops are folded in the conversion.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D87703
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/test/Dialect/Linalg/transform-patterns-matmul-to-vector.mlir
The file was modifiedmlir/test/Dialect/Vector/canonicalize.mlir
Commit 79b21fc187643416dbd21db10abe46a91b4c3f09 by Amara Emerson
[AArch64][GlobalISel] Fix bug in fewVectorElts action while legalizing oversize G_FPTRUNC vectors.

For <8 x s32> = fptrunc <8 x s64> the fewerElementsVector action tries to break
down the source vector into the final source vectors of <2 x s64> using unmerge.
This fixes a crash due to using the wrong number of elements for the breakdown
type.

Also add some legalizer tests for explicitly G_FPTRUNC which we didn't have.

Differential Revision: https://reviews.llvm.org/D87814
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
Commit 7f7993e0daf459c308747f034e3fbd73889c7ab3 by david.green
[ARM] Expand distributing increments to also handle existing pre/post inc instructions.

This extends the distributing postinc code in load/store optimizer to
also handle the case where there is an existing pre/post inc instruction,
where subsequent instructions can be modified to use the adjusted
offset from the increment. This can save us having to keep the old
register live past the increment instruction.

Differential Revision: https://reviews.llvm.org/D83377
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vst2.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vst3.ll
Commit c6ebe3fd002c1d3b903ab6e912ebd815fdb0e964 by spatel
[InstSimplify] add tests for FP constant miscompile; NFC (PR43907)
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/cast.ll
Commit 7d593d0d6905b55ca1124fca5e4d1ebb17203138 by benny.kra
[amdgpu] Compilation fix for Release

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D87838
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 1e19165bd89db6671a80e0b25b32d5c7ae79455c by ecaldas
[SyntaxTree][Synthesis] Fix allocation in `createTree` for more general use

Prior to this change `createTree` could not create arbitrary syntax
trees. Now it dispatches to the constructor of the concrete syntax tree
according to the `NodeKind` passed as argument. This allows reuse inside
the Synthesis API.  # Please enter the commit message for your changes.
Lines starting

Differential Revision: https://reviews.llvm.org/D87820
The file was modifiedclang/include/clang/Tooling/Syntax/BuildTree.h
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp
Commit 50dd545b00ed72a9ed2031cb5eb9bf26dd5af0c0 by mascasa
[DFSan] Add bcmp wrapper.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87801
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp
The file was modifiedcompiler-rt/test/dfsan/custom.cpp
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt
Commit e09107ab80dced55414fa458cf78e6cdfe90da6e by raul.tambre
[Sema] Introduce BuiltinAttr, per-declaration builtin-ness

Instead of relying on whether a certain identifier is a builtin, introduce BuiltinAttr to specify a declaration as having builtin semantics.

This fixes incompatible redeclarations of builtins, as reverting the identifier as being builtin due to one incompatible redeclaration would have broken rest of the builtin calls.
Mostly-compatible redeclarations of builtins also no longer have builtin semantics. They don't call the builtin nor inherit their attributes.
A long-standing FIXME regarding builtins inside a namespace enclosed in extern "C" not being recognized is also addressed.

Due to the more correct handling attributes for builtin functions are added in more places, resulting in more useful warnings.
Tests are updated to reflect that.

Intrinsics without an inline definition in intrin.h had `inline` and `static` removed as they had no effect and caused them to no longer be recognized as builtins otherwise.

A pthread_create() related test is XFAIL-ed, as it relied on it being recognized as a builtin based on its name.
The builtin declaration syntax is too restrictive and doesn't allow custom structs, function pointers, etc.
It seems to be the only case and fixing this would require reworking the current builtin syntax, so this seems acceptable.

Fixes PR45410.

Reviewed By: rsmith, yutsumi

Differential Revision: https://reviews.llvm.org/D77491
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/test/Sema/warn-fortify-source.c
The file was addedclang/test/CodeGen/builtin-redeclaration.c
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Headers/intrin.h
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/AST/ast-dump-attr.cpp
The file was modifiedclang/test/CodeGenCXX/builtins.cpp
The file was modifiedclang/lib/Sema/SemaLookup.cpp
The file was modifiedclang/lib/Serialization/ASTWriter.cpp
The file was modifiedclang/test/CodeGen/callback_pthread_create.c
The file was modifiedclang/test/Sema/implicit-builtin-decl.c
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/include/clang/Basic/IdentifierTable.h
The file was modifiedclang/test/SemaCXX/cxx11-compat.cpp
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was modifiedclang/lib/AST/Decl.cpp
The file was modifiedclang/test/SemaCXX/warn-unused-local-typedef.cpp
Commit fb182028361504569ff6322bfa12b12e1ab74e30 by zhuoryin
[AMDGPU] Fix ROCm unit test memref initialization
The file was modifiedmlir/test/mlir-rocm-runner/vecadd.mlir
The file was modifiedmlir/test/mlir-rocm-runner/vector-transferops.mlir
The file was modifiedmlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp
Commit dd28254063f27ed6accd8f331d292217663ebaf8 by Adrian Prantl
Add missing include
The file was modifiedllvm/include/llvm/Transforms/InstCombine/InstCombiner.h
Commit 50f1d4517ae46a43b9bd1b488cc632b65de0dbbe by Jinsong Ji
[PowerPC][AIX] Don't hardcode python invoke command line

We shouldn't assume python exists, we should let lit
to decide whether it is python or python3 and expand the path.
The file was modifiedllvm/test/CodeGen/PowerPC/aix-overflow-toc.py
Commit e06914b59bf8e2344969def6f20b394cacce186b by spatel
[VectorCombine] add test for multi-use load (PR47558); NFC
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
Commit ddd9575d15ad8f0fa746b5ece63530c4619e3e9c by spatel
[VectorCombine] rearrange bailouts for load insert for efficiency; NFC
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit 772bd8a7d99b8db899f594d393986e4b6cd85aa1 by Yaxun.Liu
Revert "[CUDA][HIP] Defer overloading resolution diagnostics for host device functions"

This reverts commit 7f1f89ec8d9944559042bb6d3b1132eabe3409de.

This reverts commit 40df06cdafc010002fc9cfe1dda73d689b7d27a6.
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/lib/Sema/SemaCUDA.cpp
The file was modifiedclang/lib/Sema/SemaExprObjC.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticFrontend.h
The file was modifiedclang/utils/TableGen/ClangDiagnosticsEmitter.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/lib/Sema/SemaTemplateVariadic.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/include/clang/Basic/DiagnosticComment.h
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/Sema/SemaAttr.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
The file was modifiedclang/tools/diagtool/DiagnosticNames.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSerialization.h
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticRefactoring.h
The file was modifiedclang-tools-extra/clangd/Diagnostics.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticLex.h
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
The file was modifiedclang/lib/Sema/AnalysisBasedWarnings.cpp
The file was removedclang/test/SemaCUDA/deferred-oeverload.cu
The file was modifiedclang/include/clang/Basic/DiagnosticAST.h
The file was modifiedclang/include/clang/Basic/DiagnosticIDs.h
The file was modifiedclang/lib/Basic/DiagnosticIDs.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticAnalysis.h
The file was modifiedclang/include/clang/Basic/DiagnosticDriver.h
The file was modifiedclang/lib/Sema/SemaStmt.cpp
The file was modifiedclang/test/TableGen/DiagnosticBase.inc
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/include/clang/Basic/Diagnostic.td
The file was modifiedclang/include/clang/Basic/DiagnosticParse.h
The file was modifiedclang/include/clang/Basic/DiagnosticSema.h
The file was modifiedclang/lib/Driver/ToolChains/Cuda.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticCrossTU.h
The file was modifiedclang/lib/Sema/SemaSYCL.cpp
The file was modifiedclang/lib/Sema/SemaStmtAsm.cpp
The file was removedclang/test/TableGen/deferred-diag.td
Commit 829d14ee0a6aa79c89f7f3d9fcd9d27d3efd2b91 by Yaxun.Liu
Revert "[NFC] Refactor DiagnosticBuilder and PartialDiagnostic"

This reverts commit ee5519d323571c4a9a7d92cb817023c9b95334cd.
The file was modifiedclang/include/clang/AST/Decl.h
The file was modifiedclang/include/clang/Sema/ParsedAttr.h
The file was modifiedclang/include/clang/AST/Type.h
The file was modifiedclang/include/clang/AST/CanonicalType.h
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/lib/AST/DeclCXX.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/AST/TemplateBase.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/include/clang/AST/NestedNameSpecifier.h
The file was modifiedclang/include/clang/AST/Attr.h
The file was modifiedclang/include/clang/AST/TemplateBase.h
The file was modifiedclang/include/clang/Basic/Diagnostic.h
The file was modifiedclang/include/clang/AST/TemplateName.h
The file was modifiedclang/include/clang/AST/DeclarationName.h
The file was modifiedclang/lib/Basic/Diagnostic.cpp
The file was modifiedclang/include/clang/AST/DeclCXX.h
The file was modifiedclang/include/clang/Basic/PartialDiagnostic.h
The file was modifiedclang/include/clang/Sema/Ownership.h
The file was modifiedclang/lib/AST/TemplateName.cpp
Commit 296e97ae8f7183c2f8737b9e6e68df4904dbfadf by uday
[MLIR] Support for return values in Affine.For yield

Add support for return values in affine.for yield along the same lines
as scf.for and affine.parallel.

Signed-off-by: Abhishek Varma <abhishek.varma@polymagelabs.com>

Differential Revision: https://reviews.llvm.org/D87437
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td
The file was modifiedmlir/test/Dialect/Affine/ops.mlir
The file was modifiedmlir/test/EDSC/builder-api-test.cpp
The file was modifiedmlir/include/mlir/Dialect/Affine/EDSC/Builders.h
The file was modifiedmlir/lib/Dialect/Affine/EDSC/Builders.cpp
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp
The file was modifiedmlir/test/Dialect/Affine/invalid.mlir
Commit 0602e8f77f8662c85155b8cf02937a2e71c01e12 by uday
[MLIR][Affine] Add parametric tile size support for affine.for tiling

Add support to tile affine.for ops with parametric sizes (i.e., SSA
values). Currently supports hyper-rectangular loop nests with constant
lower bounds only. Move methods

  - moveLoopBody(*)
  - getTileableBands(*)
  - checkTilingLegality(*)
  - tilePerfectlyNested(*)
  - constructTiledIndexSetHyperRect(*)

to allow reuse with constant tile size API. Add a test pass -test-affine
-parametric-tile to test parametric tiling.

Differential Revision: https://reviews.llvm.org/D87353
The file was modifiedmlir/test/lib/Transforms/CMakeLists.txt
The file was modifiedmlir/include/mlir/Transforms/LoopUtils.h
The file was modifiedmlir/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedmlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp
The file was addedmlir/test/lib/Transforms/TestAffineLoopParametricTiling.cpp
The file was addedmlir/test/Dialect/Affine/loop-tiling-parametric.mlir
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp
Commit 3783d3bc7b3dd966ac3b9436b73f16f855d12ff2 by craig.topper
[X86] Don't match x87 register inline asm constraints unless the VT is floating point or its a clobber

The register class picked will be the RFP80 register class which has a f80 VT. The code in SelectionDAGBuilder that generates copies around inline assembly doesn't know how to handle an integer and floating point type of different bit widths.

The test case is derived from this https://godbolt.org/z/sEa659 which gcc accepts but clang crashes on. This patch just gives a more graceful error. I'm not sure if the single element struct case is special in gcc. Adding another field to the struct makes gcc reject it. If we want to support this correctly I think we need a change in the frontend to give us the true element type. Right now the frontend just realizes the constraint can take a memory argument so creates an integer type of the same size and bitcasts.

Differential Revision: https://reviews.llvm.org/D87485
The file was addedllvm/test/CodeGen/X86/asm-reject-x87-int.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 48a23bccf3732e1480ad169bd4a08a68bb100bfa by spatel
[VectorCombine] limit load+insert transform to one-use

As discussed in:
https://llvm.org/PR47558
...there are several potential fixes/follow-ups visible
in the test case, but this is the quickest and safest
fix of the perf regression.
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
Commit bea7749d0364a8c694f236a97d58167a33efdb9e by Amara Emerson
[AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal for shifts.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
Commit 7d5b10348371644c69041965b9864886e9961ddd by Amara Emerson
[AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b.

In order to not unnecessarily promote the source vector to greater than our
native vector size of 128b, I've added some cascading rules to widen based on
the number of elements.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit 1e5b7e91aa64c267e495cb4bd8351b1840694437 by rnk
[PDB] Split TypeServerSource and extend type index map lifetime

Extending the lifetime of these type index mappings does increase memory
usage (+2% in my case), but it decouples type merging from symbol
merging. This is a pre-requisite for two changes that I have in mind:
- parallel type merging: speeds up slow type merging
- defered symbol merging: avoid heap allocating (relocating) all symbols

This eliminates CVIndexMap and moves its data into TpiSource. The maps
are also split into a SmallVector and ArrayRef component, so that the
ipiMap can alias the tpiMap for /Z7 object files, and so that both maps
can simply alias the PDB type server maps for /Zi files.

Splitting TypeServerSource establishes that all input types to be merged
can be identified with two 32-bit indices:
- The index of the TpiSource object
- The type index of the record
This is useful, because this information can be stored in a single
64-bit atomic word to enable concurrent hashtable insertion.

One last change is that now all object files with debugChunks get a
TpiSource, even if they have no type info. This avoids some null checks
and special cases.

Differential Revision: https://reviews.llvm.org/D87736
The file was modifiedlld/COFF/DebugTypes.h
The file was modifiedlld/COFF/DebugTypes.cpp
The file was modifiedlld/COFF/TypeMerger.h
The file was modifiedlld/COFF/PDB.cpp
The file was modifiedlld/COFF/InputFiles.cpp
Commit a35c7f30769b4bc3745796af58c932f303a014e1 by mcinally
[SVE][WIP] Implement lowering for fixed length VSELECT to Scalable

Map fixed length VSELECT to its Scalable equivalent.

Differential Revision: https://reviews.llvm.org/D85364
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit 7e4c6fb854660318dc31ecb9842f6cfebb18c8e0 by andrew_litteken
[IRSim] Adding IR Instruction Mapper

This introduces the IRInstructionMapper, and the associated wrapper for
instructions, IRInstructionData, that maps IR level Instructions to
unsigned integers.

Mapping is done mainly by using the "isSameOperationAs" comparison
between two instructions.  If they return true, the opcode, result type,
and operand types of the instruction are used to hash the instruction
with an unsigned integer.  The mapper accepts instruction ranges, and
adds each resulting integer to a list, and each wrapped instruction to
a separate list.

At present, branches, phi nodes are not mapping and exception handling
is illegal.  Debug instructions are not considered.

The different mapping schemes are tested in
unittests/Analysis/IRSimilarityIdentifierTest.cpp

Recommit of: b04c1a9d3127730c05e8a22a0e931a12a39528df

Differential Revision: https://reviews.llvm.org/D86968
The file was modifiedllvm/unittests/Analysis/CMakeLists.txt
The file was addedllvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
The file was addedllvm/lib/Analysis/IRSimilarityIdentifier.cpp
The file was addedllvm/include/llvm/Analysis/IRSimilarityIdentifier.h
The file was modifiedllvm/lib/Analysis/CMakeLists.txt
Commit 667762c64e0b2925112037c197709402b4f2221d by llvmgnsyncbot
[gn build] Port 7e4c6fb8546
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
Commit c145a1ca2593e3b8b79687d5ba8c3230c41b5130 by jonathan_roelofs
AArch64::ArchKind's underlying type is uint64_t
The file was modifiedclang/lib/Driver/ToolChains/Arch/AArch64.cpp
The file was modifiedllvm/include/llvm/Support/AArch64TargetParser.h
The file was modifiedllvm/lib/Support/AArch64TargetParser.cpp
The file was modifiedllvm/unittests/Support/TargetParserTest.cpp
Commit 5813fca1076089c835de737834955a0fe7eb3898 by Vitaly Buka
[Lsan] Use fp registers to search for pointers

X86 can use xmm registers for pointers operations. e.g. for std::swap.
I don't know yet if it's possible on other platforms.

NT_X86_XSTATE includes all registers from NT_FPREGSET so
the latter used only if the former is not available. I am not sure how
reasonable to expect that but LLD has such fallback in
NativeRegisterContextLinux_x86_64::ReadFPR.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D87754
The file was addedcompiler-rt/test/lsan/TestCases/use_registers_extra.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
The file was modifiedcompiler-rt/test/lsan/TestCases/use_registers.cpp
Commit a4bb71b1c0d9952208ad32bc4992cc211d43c5bb by wei.huang
Disable hoisting MI to hotter basic blocks when using pgo

This is a follow up patch for https://reviews.llvm.org/D63676 to
enable the feature when using pgo.

Differential Revision: https://reviews.llvm.org/D85240
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/lib/CodeGen/MachineLICM.cpp
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/X86/opt-pipeline.ll
Commit 51973a607dfa4681037aff43e295f3ea1fb0f3f4 by flo
[SCEV] Add test cases for max BTC with loop guard info.

This adds test cases for PR40961 and PR47247. They illustrate cases in
which the max backedge-taken count can be improved by information from
the loop guards.
The file was addedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
Commit 59855b9d3bacc4321e3dd22ccf09bd9d177fdb6f by nikita.ppv
[GVN] Add additional assume tests (NFC)

The other assume tests seem to be dealing with equalities in
particular. Test implication for the condition itself, especially
the negated case from PR47496.
The file was addedllvm/test/Transforms/GVN/assume.ll
Commit 91ce8e121b7f24ef68fad0ab07f6ab7e1ee06855 by nikita.ppv
[GVN] Use that assume(!X) implies X==false (PR47496)

We already use that assume(X) implies X==true, do the same for
assume(!X) implying X==false. This fixes PR47496.
The file was modifiedllvm/lib/Transforms/Scalar/GVN.cpp
The file was modifiedllvm/test/Transforms/GVN/assume.ll
Commit 1cee33e9dbb6c30ff1dd30453a263696bfccfd8a by whitneyt
[LoopUnrollAndJam] Allow unroll and jam loops forced by user.

Summary: Allow unroll and jam loops forced by user.
LoopUnrollAndJamPass is still disabled by default in the NPM pipeline,
and can be controlled by -enable-npm-unroll-and-jam.

Reviewed By: Meinersbur, dmgreen

Differential Revision: https://reviews.llvm.org/D87786
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/pragma-explicit.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
Commit 05d4c4ebc2fb006b8a2bd05b24c6aba10dd2eef8 by nikita.ppv
[InstCombine] Canonicalize SPF_ABS to abs intrinc

Enable canonicalization of SPF_ABS and SPF_NABS to the abs intrinsic.

To be conservative, the one-use check on the comparison is retained,
this may be relaxed if all goes well.

It's pretty likely that this will uncover places that missing
handling for the abs() intrinsic. Please report any seen performance
regressions.

Differential Revision: https://reviews.llvm.org/D87188
The file was modifiedllvm/test/Transforms/InstCombine/abs-1.ll
The file was modifiedllvm/test/Transforms/InstCombine/call-callconv.ll
The file was modifiedllvm/test/Transforms/InstCombine/sub-of-negatible.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/select_meta.ll
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll
The file was modifiedllvm/test/Transforms/InstCombine/abs_abs.ll
The file was modifiedllvm/test/Transforms/InstCombine/cttz-abs.ll
The file was modifiedllvm/test/Transforms/InstCombine/max-of-nots.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
Commit 53ba045f488f7ef7d4894926fad8de0b76f1e20a by alexshap
[llvm-install-name-tool] Update the command-line guide
The file was modifiedllvm/docs/CommandGuide/llvm-install-name-tool.rst
Commit 179a22e807a40ae5821920cec3c1933eef4dc30c by aeubanks
[NewPM] Fix pr45927.ll under NPM
The file was modifiedllvm/test/Analysis/MemorySSA/pr45927.ll
Commit a0017c2bc258690146f18491317144e487ddb101 by flo
[MemorySSA] Be more conservative when traversing MemoryPhis.

I think we need to be even more conservative when traversing memory
phis, to make sure we catch any loop carried dependences.

This approach updates fillInCurrentPair to use unknown sizes for
locations when we walk over a phi, unless the location is guaranteed to
be loop-invariant for any possible loop. Using an unknown size for
locations should ensure we catch all memory accesses to locations after
the given memory location, which includes loop-carried dependences.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D87778
The file was modifiedllvm/test/Analysis/MemorySSA/phi-translation.ll
The file was modifiedllvm/include/llvm/Analysis/MemorySSA.h
Commit 0ff28fa6a75617d61b1aeea77463d6a1684c3c89 by dschuff
Support dwarf fission for wasm object files

Initial support for dwarf fission sections (-gsplit-dwarf) on wasm.
The most interesting change is support for writing 2 files (.o and .dwo) in the
wasm object writer. My approach moves object-writing logic into its own function
and calls it twice, swapping out the endian::Writer (W) in between calls.
It also splits the import-preparation step into its own function (and skips it when writing a dwo).

Differential Revision: https://reviews.llvm.org/D85685
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp
The file was modifiedclang/test/Driver/split-debug.c
The file was modifiedllvm/lib/MC/MCAsmBackend.cpp
The file was modifiedllvm/lib/MC/WasmObjectWriter.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was addedllvm/test/DebugInfo/WebAssembly/fission-sections.ll
The file was addedllvm/test/DebugInfo/WebAssembly/fission-cu.ll
The file was modifiedllvm/include/llvm/MC/MCWasmObjectWriter.h
Commit 99e865b618f31c69776273a60addbd88917a29d9 by qcolombet
[TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator

Before this patch, the last chance recoloring and deferred spilling
techniques were solely controled by command line options.
This patch adds target hooks for these two techniques so that it
is easier for backend writers to override the default behavior.

The default behavior of the hooks preserves the default values of
the related command line options.

NFC
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h
Commit f2f0474c93ee67421fae007528ae4be20ae384f8 by aeubanks
[test] Fix FullUnroll.ll

I believe the intention of this test added in
https://reviews.llvm.org/D71687 was to test LoopFullUnrollPass with
clang's -fno-unroll-loops, not its interaction with optnone. Loop
unrolling passes don't run under optnone/-O0.

Also added back unintentionally removed -disable-loop-unrolling from
https://reviews.llvm.org/D85578.

Reviewed By: echristo

Differential Revision: https://reviews.llvm.org/D86485
The file was modifiedllvm/test/Transforms/LoopUnroll/FullUnroll.ll
Commit b04c181ed776c344e6f5e2653a22bc6e5746834a by listmail
[AArch64] Enable implicit null check transformation

This change enables the generic implicit null transformation for the AArch64 target. As background for those unfamiliar with our implicit null check support:

    An implicit null check is the use of a signal handler to catch and redirect to a handler a null pointer. Specifically, it's replacing an explicit conditional branch with such a redirect. This is only done for very cold branches under frontend control w/appropriate metadata.
    FAULTING_OP is used to wrap the faulting instruction. It is modelled as being a conditional branch to reflect the fact it can transfer control in the CFG.
    FAULTING_OP does not need to be an analyzable branch to achieve it's purpose. (Or at least, that's the x86 model. I find this slightly questionable.)
    When lowering to MC, we convert the FAULTING_OP back into the actual instruction, record the labels, and lower the original instruction.

As can be seen in the test changes, currently the AArch64 backend does not eliminate the unconditional branch to the fallthrough block. I've tried two approaches, neither of which worked. I plan to return to this in a separate change set once I've wrapped my head around the interactions a bit better. (X86 handles this via AllowModify on analyzeBranch, but adding the obvious code causing BranchFolding to crash. I haven't yet figured out if it's a latent bug in BranchFolding, or something I'm doing wrong.)

Differential Revision: https://reviews.llvm.org/D87851
The file was modifiedllvm/lib/CodeGen/BranchRelaxation.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/lib/CodeGen/ImplicitNullChecks.cpp
The file was modifiedllvm/test/CodeGen/AArch64/implicit-null-check.ll
Commit 1c466477ad468d8a18c43b738df7b7fc6213e9a8 by zhaoshiz
[RISCV] Support Shadow Call Stack

Currenlty assume x18 is used as pointer to shadow call stack. User shall pass
flags:

"-fsanitize=shadow-call-stack -ffixed-x18"

Runtime supported is needed to setup x18.

If SCS is desired, all parts of the program should be built with -ffixed-x18 to
maintain inter-operatability.

There's no particuluar reason that we must use x18 as SCS pointer. Any register
may be used, as long as it does not have designated purpose already, like RA or
passing call arguments.

Differential Revision: https://reviews.llvm.org/D84414
The file was modifiedclang/test/Driver/sanitizer-ld.c
The file was modifiedclang/lib/Driver/SanitizerArgs.cpp
The file was modifiedclang/test/CodeGen/shadowcallstack-attr.c
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/shadowcallstack.ll
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was modifiedclang/lib/Driver/ToolChain.cpp
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
Commit 8069844577d47f503cb71644f2e58e0237d5b539 by jurahul
[MLIR][TableGen] Automatic detection and elimination of redundant methods

- Change OpClass new method addition to find and eliminate any existing methods that
  are made redundant by the newly added method, as well as detect if the newly added
  method will be redundant and return nullptr in that case.
- To facilitate that, add the notion of resolved and unresolved parameters, where resolved
  parameters have each parameter type known, so that redundancy checks on methods
  with same name but different parameter types can be done.
- Eliminate existing code to avoid adding conflicting/redundant build methods and rely
  on this new mechanism to eliminate conflicting build methods.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47095

Differential Revision: https://reviews.llvm.org/D87059
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/include/mlir/TableGen/OpClass.h
The file was modifiedmlir/test/mlir-tblgen/op-attribute.td
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
The file was modifiedmlir/lib/TableGen/OpClass.cpp
The file was modifiedmlir/test/mlir-tblgen/op-result.td
Commit b4013f9c7febe70bddca16fb80a2e99623528871 by listmail
[MemorySSA] Fix an unused variable warning [NFC]
The file was modifiedllvm/include/llvm/Analysis/MemorySSA.h
Commit 2c3bc918db35913437e9302b77b11c08eb3ea6e4 by amy.kwan1
[PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

This patch implements the vec_cntm function prototypes in altivec.h in order to
utilize the vector count mask bits instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82726
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
Commit 6f3c0991bf9be48bd18a324c90e4cfcd37f82b96 by amy.kwan1
[PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests

This patch adds the instruction definitions and assembly/disassembly tests for
the set boolean condition instructions. This also includes the negative, and
reverse variants of the instruction.

Differential Revision: https://reviews.llvm.org/D86252
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
Commit 196e2f97b714bb535a39a2daa949e523c21c0269 by Amara Emerson
[AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit f5898f8c2def7a1897559a7454086243b7e9ebb6 by Amara Emerson
[AArch64][GlobalISel] Make G_STORE <8 x s8> legal.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit 4926a5ee63017396e1c55b1505f9fd2bed858218 by Vedant Kumar
[lldb] Clarify docstring for SBBlock::IsInlined, NFC

Previously, there was a little ambiguity about whether IsInlined should
return true for an inlined lexical block, since technically the lexical
block would not represent an inlined function (it'd just be contained
within one).

Edit suggested by Jim Ingham.
The file was modifiedlldb/bindings/interface/SBBlock.i
Commit bae63742057785e03732f58d6ed1ec7bda090cc1 by silvasean
[mlir][shape] Add `shape.cstr_require %bool`

This op is a catch-all for creating witnesses from various random kinds
of constraints. In particular, I when dealing with extents directly,
which are of `index` type, one can directly use std ops for calculating
the predicates, and then use cstr_require for the final conversion to a
witness.

Differential Revision: https://reviews.llvm.org/D87871
The file was modifiedmlir/test/Dialect/Shape/ops.mlir
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp
The file was modifiedmlir/test/Dialect/Shape/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
Commit ea237e2c8e5d082715effb9cb64158d7c6894e27 by jurahul
[MLIR] Fix build failure due to https://reviews.llvm.org/D87059.

- Remove spurious ;
- Make comparison object invokable as const.

Differential Revision: https://reviews.llvm.org/D87872
The file was modifiedmlir/include/mlir/TableGen/OpClass.h
Commit 27f34540ea56207f527dba6bbb9cd25a57be3f62 by mcgrathr
[scudo/standalone] Don't define test main function for Fuchsia

Fuchsia's unit test library provides the main function by default.

Reviewed By: cryptoad

Differential Revision: https://reviews.llvm.org/D87809
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/scudo_unit_test_main.cpp
Commit 03358becbf22a221d6d965ec8f3f7068668f7d29 by Vitaly Buka
[NFC][Lsan] Fix zero-sized array compilation error
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp
Commit 55edf7039e22312790ac950305746262d2856d97 by Vitaly Buka
[NFC] clang-format one line
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp