SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [tools][remarks-shlib] Don't build libRemarks.so without PIC (details)
  2. [X86] Rename combineExtInVec to combineEXTEND_VECTOR_INREG. NFCI. (details)
  3. [MemLoc] Support lllvm.memcpy.inline in MemoryLocation::getForArgument (details)
  4. JSONCompilationDatabase.cpp - cleanup key parsing error checks. NFCI. (details)
  5. [X86] combineX86ShufflesRecursively - fix use after move warning. NFCI. (details)
  6. DWARFYAML::emitDebugSections - fix use after std::move warnings. NFCI. (details)
  7. [X86] Rename getExtendInVec to getEXTEND_VECTOR_INREG. NFCI. (details)
  8. [X86][SSE] Enable ZERO_EXTEND_VECTOR_INREG shuffle combining on SSE41 targets. (details)
  9. [X86][SSE] Fold EXTEND_VECTOR_INREG(EXTEND_VECTOR_INREG(X)) -> EXTEND_VECTOR_INREG(X) (details)
  10. [Diagnostics] Fixed -Wsizeof-array-div false positive when divisor is sizeof reference type (PR47495) (details)
  11. [InstCombine] replace zombie unreachable values with 'undef' before erasing (details)
  12. [InstCombine] factorize left shifts of add/sub (details)
  13. [X86][SSE] Fold SIGN_EXTEND(SIGN_EXTEND_VECTOR_INREG(X)) -> SIGN_EXTEND_VECTOR_INREG(X) (details)
  14. [X86][SSE] Fold EXTEND_VECTOR_INREG(EXTRACT_SUBVECTOR(EXTEND(X),0)) -> EXTEND_VECTOR_INREG(X) (details)
  15. [LVI] Refactor getValueFromICmpCondition (NFC) (details)
  16. [CVP] Add tests for mask comparisons (NFC) (details)
  17. [LVI] Get value range from mask comparison (details)
  18. [CVP] Additional tests for comparison with offset (NFC) (details)
  19. [ARM] Constant fold VMOVrh (details)
  20. [X86] Add 32-bit command lines to masked_store.ll and masked_load.ll (details)
  21. [X86] Stop reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore from creating scalar i64 load/stores in 32-bit mode (details)
Commit 26947d7b63809413b96b0bb6033f168488836289 by ro
[tools][remarks-shlib] Don't build libRemarks.so without PIC

A build on `sparcv9-sun-solaris2.11` with `-DLLVM_ENABLE_PIC=Off` failed
linking `libRemarks.so`:

  [27/2297] Linking CXX shared library lib/libRemarks.so.12git
  FAILED: lib/libRemarks.so.12git
  [...]
  ld: fatal: relocation error: R_SPARC_H44: file lib/libLLVMRemarks.a(Remark.cpp.o): symbol _ZTVN4llvm18raw_string_ostreamE: invalid shared object relocation type: ABS44 code model unsupported
  [...]

On Solaris/sparcv9 as on many other targets you cannot link non-PIC objects
into a shared object.

The following patch avoids this by not building the library with PIC.  It
allowed the build to complete and `ninja check-all` showed no errors.

Differential Revision: https://reviews.llvm.org/D85626
The file was modifiedllvm/tools/remarks-shlib/CMakeLists.txt
Commit e17686ae60faa85857e61052632bb6e6c0230ae0 by llvm-dev
[X86] Rename combineExtInVec to combineEXTEND_VECTOR_INREG. NFCI.

Make it easier to find the method by naming it after the ops it actually handles. We already do this for lowering.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2990518b0324eedca455b2bbf93b69f287dd6d52 by Dávid Bolvanský
 [MemLoc] Support lllvm.memcpy.inline in MemoryLocation::getForArgument

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D87971
The file was modifiedllvm/lib/Analysis/MemoryLocation.cpp
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memintrinsics.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memset-and-memcpy.ll
Commit a735d6eae2847b039d12c75d4c794862dad59bc1 by llvm-dev
JSONCompilationDatabase.cpp - cleanup key parsing error checks. NFCI.

Merge the key + sequence/value checks with the key handling code.

Reduces the number of key string comparisons and avoids a number of clang static analyzer null dereference warnings.
The file was modifiedclang/lib/Tooling/JSONCompilationDatabase.cpp
Commit 91720ee561b2da4161df6abaddfd8a677aebb504 by llvm-dev
[X86] combineX86ShufflesRecursively - fix use after move warning. NFCI.

After moving WidenedMask is in an undefined state, so reduce scope of the variable so its reinitialized every iteration - we should still retain any memory allocation savings.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 6bb912336804822cc4b09f6849f1fd7d12057132 by llvm-dev
DWARFYAML::emitDebugSections - fix use after std::move warnings. NFCI.

We were using Err after it had been moved into cantFail - avoid this by calling cantFail with Error::success() directly.
The file was modifiedllvm/lib/ObjectYAML/DWARFEmitter.cpp
Commit 2b634a9d0e144a619ba68fc064dab0771f725063 by llvm-dev
[X86] Rename getExtendInVec to getEXTEND_VECTOR_INREG. NFCI.

Make it easier to find the method by naming it after the ops it actually handles. We already do this for lowering/combining.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit a0c8793ce691d77453bca9d31b0031d39d07a5b4 by llvm-dev
[X86][SSE] Enable ZERO_EXTEND_VECTOR_INREG shuffle combining on SSE41 targets.

Allows ZERO_EXTEND_VECTOR_INREG to be shuffle combined on all targets where it is legal.
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
The file was modifiedllvm/test/CodeGen/X86/pmulh.ll
The file was modifiedllvm/test/CodeGen/X86/2011-12-28-vselecti8.ll
The file was modifiedllvm/test/CodeGen/X86/slow-pmulld.ll
The file was modifiedllvm/test/CodeGen/X86/vector-pcmp.ll
The file was modifiedllvm/test/CodeGen/X86/cast-vsel.ll
The file was modifiedllvm/test/CodeGen/X86/vector-zext.ll
The file was modifiedllvm/test/CodeGen/X86/vec_int_to_fp.ll
The file was modifiedllvm/test/CodeGen/X86/widen_conv-4.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
The file was modifiedllvm/test/CodeGen/X86/pmul.ll
Commit 15c8306056beefa61533a895e8d836db72fccd14 by llvm-dev
[X86][SSE] Fold EXTEND_VECTOR_INREG(EXTEND_VECTOR_INREG(X)) -> EXTEND_VECTOR_INREG(X)

It should be possible to make this generic, but we're not great at checking legality of *_EXTEND_VECTOR_INREG ops so I'm conservatively putting this inside X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/masked_load.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2ae182258c49724e4daaae196de829ea65c116e8 by Dávid Bolvanský
[Diagnostics] Fixed -Wsizeof-array-div false positive when divisor is sizeof reference type (PR47495)
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/Sema/div-sizeof-array.cpp
Commit cf75e83275d16f9172fa5ab448a981afdadd34d0 by spatel
[InstCombine] replace zombie unreachable values with 'undef' before erasing

The test (currently crashing) is reduced from the example provided
in the post-commit discussion in D87149.

Differential Revision: https://reviews.llvm.org/D87965
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/test/Transforms/InstCombine/phi.ll
Commit 7903ae4720a8c4f3c694954d56293c7507e07945 by spatel
[InstCombine] factorize left shifts of add/sub

We do similar factorization folds in SimplifyUsingDistributiveLaws,
but that drops no-wrap properties. Propagating those optimally may
help solve:
https://llvm.org/PR47430

The propagation is all-or-nothing for these patterns: when all
3 incoming ops have nsw or nuw, the 2 new ops should have the
same no-wrap property:
https://alive2.llvm.org/ce/z/Dv8wsU

This also solves:
https://llvm.org/PR47584
The file was modifiedllvm/test/Transforms/InstCombine/shl-factor.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
Commit bb0078e5911a8cd7742c99c391ccea802f02e22e by llvm-dev
[X86][SSE] Fold SIGN_EXTEND(SIGN_EXTEND_VECTOR_INREG(X)) -> SIGN_EXTEND_VECTOR_INREG(X)

It should be possible to make this generic, but we're not great at checking legality of *_EXTEND_VECTOR_INREG ops so I'm conservatively putting this inside X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/masked_load.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 0bfeede669f0d9c051344977805005c98e8cb41d by llvm-dev
[X86][SSE] Fold EXTEND_VECTOR_INREG(EXTRACT_SUBVECTOR(EXTEND(X),0)) -> EXTEND_VECTOR_INREG(X)
The file was modifiedllvm/test/CodeGen/X86/min-legal-vector-width.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit f94bbe19b6f6086ff94b1eb4ef0bc5802752bfe1 by nikita.ppv
[LVI] Refactor getValueFromICmpCondition (NFC)

Rewrite this in a way where the core logic is in a separate
function, that is invoked with swapped operands. This makes it
easier to add handling for additional icmp patterns.
The file was modifiedllvm/lib/Analysis/LazyValueInfo.cpp
Commit 91af6a78d00f731826ff2eb81c9a9281b1d21388 by nikita.ppv
[CVP] Add tests for mask comparisons (NFC)
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/icmp.ll
Commit 445db89b537e5397a2d4b08e79751edb845b2c2a by nikita.ppv
[LVI] Get value range from mask comparison

InstCombine likes to canonicalize comparisons of the form
X == C || X == C+1 into (X & -2) == C'. Make sure LVI can still
recover the value range from this. Can of course also be useful
for proper mask comparisons.

For the sake of clarity, the implementation goes through KnownBits
to compute the range.
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/icmp.ll
The file was modifiedllvm/lib/Analysis/LazyValueInfo.cpp
Commit 1a2723809839a888f03ba69e36a358ba18c0c8ae by nikita.ppv
[CVP] Additional tests for comparison with offset (NFC)

Both icmps have an additional offset here. We would fold this if
the second one didn't.
The file was modifiedllvm/test/Transforms/CorrelatedValuePropagation/icmp.ll
Commit 29bd8ea11091d996d166257e07bf2308651d284d by david.green
[ARM] Constant fold VMOVrh

This adds simple constant folding for VMOVrh, to constant fold fp16
constants to integer values. It can help especially with soft calling
conventions, but some of the results are not optimal as we end up
loading using a vldr. This will be improved in a follow up patch.

Differential Revision: https://reviews.llvm.org/D87789
The file was modifiedllvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/ARM/fp16-bitcast.ll
Commit 9b1c98c0fbe2d7fdc22debd3e7d1fcf44952a0ce by craig.topper
[X86] Add 32-bit command lines to masked_store.ll and masked_load.ll
The file was modifiedllvm/test/CodeGen/X86/masked_load.ll
The file was modifiedllvm/test/CodeGen/X86/masked_store.ll
Commit 4e8c028158b56d9c2142a62464e8e0686bde3584 by craig.topper
[X86] Stop reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore from creating scalar i64 load/stores in 32-bit mode

If we emit a scalar i64 load/store it will get type legalized to two i32 load/stores.

Differential Revision: https://reviews.llvm.org/D87862
The file was modifiedllvm/test/CodeGen/X86/masked_load.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp