SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. Added x86_64-fedora-clang builder and fedora-llvm-x86_64 slave (details)
  2. Name builddir of x86_64-fedora-clang builder like the slave/worker fedora-llvm-x86_64 (details)
  3. clang-x86-ninja-win10 fixed slash replacement (details)
  4. clang-x86-ninja-win10 fixed MSVC version output (details)
  5. [zorg] [PowerPC] set lld as the default linker on ppc64le-clang-rhel bot (details)
Commit d5933da06ce30de8cfec8ea57f8ecce0d094cb9c by kkleine
Added x86_64-fedora-clang builder and fedora-llvm-x86_64 slave

I'm evaluating how to run a buildbot slave/worker in a Red Hat internal OpenShift cluster.

Differential Revision: https://reviews.llvm.org/D88007
The file was modifiedbuildbot/osuosl/master/config/builders.py
The file was modifiedbuildbot/osuosl/master/config/slaves.py
Commit 5bf9586c573c6057a05f486c014e0268e173af9c by kkleine
Name builddir of x86_64-fedora-clang builder like the slave/worker fedora-llvm-x86_64
The file was modifiedbuildbot/osuosl/master/config/builders.py
Commit 3d28ab15412b056861c65d2e899507138e9e8985 by kuhnel
clang-x86-ninja-win10 fixed slash replacement

now only replacing slashes in lines that define paths
The file was addedbuildbot/google/docker/buildbot-windows10-vs2019/fix_buildbot_tac_paths.py
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/run.ps1
The file was modifiedbuildbot/google/terraform/main.tf
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/Dockerfile
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/VERSION
Commit c3a4cac8157da0a80a35460fcc14791c89f14c17 by kuhnel
clang-x86-ninja-win10 fixed MSVC version output
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/run.ps1
Commit f6a1fc1366bd977313c9e332c54357b297959d6b by saghir
[zorg] [PowerPC] set lld as the default linker on ppc64le-clang-rhel bot

This patch sets lld as the default linker for ppc64le-clang-rhel-test
buildbot.

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D87993
The file was modifiedbuildbot/osuosl/master/config/builders.py

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [ThinLTO] Avoid temporaries when loading global decl attachment metadata (details)
  2. [lld-maco] fix build breakage (details)
  3. [Sanitizers] Fix test case that doesn't clean up after itself (details)
  4. [sanitizers] Remove the message queue with IPC_RMID after D82897 (details)
  5. [RISCV][ASAN] updated platform macros to simplify detection of RISCV64 platform (details)
  6. [Analyzer][WebKit] Use tri-state types for relevant predicates (details)
  7. [RISCV][ASAN] implementation of internal syscalls wrappers for riscv64 (details)
  8. [RISCV][ASAN] implementation of clone interceptor for riscv64 (details)
  9. [RISCV][ASAN] implementation for vfork interceptor for riscv64 (details)
  10. [RISCV][ASAN] implementation of ThreadSelf  for riscv64 (details)
  11. Add a dump() method on the pass manager for debugging purpose (NFC) (details)
  12. [MC] [Win64EH] Try to generate packed unwind info where possible (details)
  13. [InstCombine] Add parentheses in assert to silence GCC warning. NFC. (details)
  14. [CVP] Remove a redundant trailing semicolon, fixing GCC warnings. NFC. (details)
  15. [PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins (details)
  16. Revert "[RISCV][ASAN] implementation of ThreadSelf  for riscv64" (details)
  17. [NFC] Reformat preprocessor directives (details)
  18. [RISCV][ASAN] implementation of ThreadSelf  for riscv64 (details)
  19. [mlir][Linalg] Add pattern to fold linalg.tensor_reshape that add unit extent dims. (details)
  20. [AMDGPU] Fix merging m0 inits (details)
  21. [SVE] Fix InstCombinerImpl::PromoteCastOfAllocation for scalable vectors (details)
  22. Revert "[libc++] Implement LWG1203" (details)
  23. [SVE] Make EVT::getScalarSizeInBits and others consistent with Type::getScalarSizeInBits (details)
  24. [analyzer][StdLibraryFunctionsChecker] Fix getline/getdelim signatures (details)
  25. [analyzer][StdLibraryFunctionsChecker] Separate the signature from the summaries (details)
  26. [llvm-readelf/obj] - Cleanup the code. NFCI. (details)
  27. [AMDGPU] Insert waitcnt after returning from call (details)
  28. [llvm-readelf/obj] - Print section symbol names properly when dumping relocations. (details)
  29. [llvm-readelf/obj] - Fix extended section symbol indices printed in warnings for MIPS GOT/PLT entries. (details)
  30. [SVE][CodeGen] Lower legal integer -> floating point conversions (details)
  31. [flang] CHARACTER(*) return does not require explicit interface (details)
  32. [CUDA][HIP] Fix static device var used by host code only (details)
  33. [OpenMP][flang]Lower NUM_THREADS clause for parallel construct (details)
  34. [mlir] Added support for f64 memref printing in runner utils (details)
  35. [flang] Removed OpenMP lowering unittests (details)
  36. [NFCI][flang] Renamed a variable name to a more descriptive name (details)
  37. [libc++] Re-apply fdc41e11f (LWG1203) without breaking the C++11 build (details)
  38. [lldb] Fix GetRemoteSharedModule fallback logic (details)
  39. AMDGPU: Check global FP atomics match default FP mode (details)
  40. GlobalISel: Fix truncating shift amount in trunc (shl) combine (details)
  41. Fix typos in ASTMatchers.h; NFC (details)
  42. [NFC][ARM] Pre-commit tail predication test (details)
  43. [SystemZ] Make sure not to call getZExtValue on a >64 bit constant. (details)
  44. [mlir] Fix typos in Dialect.h. NFC. (details)
  45. [VPlan] Disconnect VPValue and VPUser. (details)
  46. [SVE] Lower fixed length ISD::VECREDUCE_ADD to Scalable (details)
  47. [clangd] Refactor code completion signal's utility properties. (details)
  48. [docs][llvm] Fix typos (details)
  49. [mlir][openacc] Use OptionalParseResult in loop op parser instead of bool variables (details)
Commit ab1b4810b55279bcf6fdd87be74a403440be3991 by tejohnson
[ThinLTO] Avoid temporaries when loading global decl attachment metadata

When performing ThinLTO importing, the metadata loader attempts to lazy
load, by building an index. However, module level global decl attachment
metadata was being parsed early while building the index, since the
associated (module level) global values aren't materialized on demand.
This results in the creation of forward reference temporary metadatas,
which are expensive.

Normally, these module level global values don't have much attached
metadata. However, in the case of -fwhole-program-vtables (e.g. for
whole program devirtualization), the vtables may have many attached type
metadatas. This was resulting in very slow performance when performing
ThinLTO importing with the default lazy loading.

This patch restructures the handling of these global decl attachment
records, delaying their parsing until after the lazy loading index has
been built. Then the parser can use the interface that loads from the
index, which resolves forward references immediately instead of creating
expensive temporaries.

For one ThinLTO backend that imports from modules containing huge
numbers of vtables and associated types, I measured the following
compile times for the metadata materialization during function
importing, rounded to nearest second:

No -fwhole-program-vtables:
  Lazy loading on (head):  1s
  Lazy loading off (head): 3s
  Lazy loading on (patch): 1s

With -fwhole-program-vtables:
  Lazy loading on (head):  440s
  Lazy loading off (head): 4s
  Lazy loading on (patch): 2s

Differential Revision: https://reviews.llvm.org/D87970
The file was modifiedllvm/lib/Bitcode/Reader/MetadataLoader.cpp
The file was modifiedllvm/test/ThinLTO/X86/devirt2.ll
Commit ab903560a466194d4350600ad946934eb72f1a14 by gkm
[lld-maco] fix build breakage
The file was modifiedlld/MachO/Writer.cpp
Commit f1746be66673bc2b59f7aaad1c6a7938ed98194b by nemanja.i.ibm
[Sanitizers] Fix test case that doesn't clean up after itself

Commit https://reviews.llvm.org/rG144e57fc9535 added this test
case that creates message queues but does not remove them. The
message queues subsequently build up on the machine until the
system wide limit is reached. This has caused failures for a
number of bots running on a couple of big PPC machines.

This patch just adds the missing cleanup.
The file was modifiedcompiler-rt/test/sanitizer_common/TestCases/Linux/sysmsg.c
Commit cabe31f415054b45b4fa6c17e4ddf09cc39bf4e8 by i
[sanitizers] Remove the message queue with IPC_RMID after D82897
The file was modifiedcompiler-rt/test/sanitizer_common/TestCases/Linux/sysmsg.c
Commit dfd295431a50aa8bccc0b89da9acf3c48b3d4b29 by Vitaly Buka
[RISCV][ASAN] updated platform macros to simplify detection of RISCV64 platform

[2/11] patch series to port ASAN for riscv64

Depends On D87997

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87998
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
Commit 47e6851423fd32f0685a643236ad946e23ab14ff by Jan Korous
[Analyzer][WebKit] Use tri-state types for relevant predicates

Some of the predicates can't always be decided - for example when a type
definition isn't available. At the same time it's necessary to let
client code decide what to do about such cases - specifically we can't
just use true or false values as there are callees with
conflicting strategies how to handle this.

This is a speculative fix for PR47276.

Differential Revision: https://reviews.llvm.org/D88133
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/RefCntblBaseVirtualDtorChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
The file was modifiedclang/lib/StaticAnalyzer/Checkers/WebKit/NoUncountedMembersChecker.cpp
Commit 6c22d00d7896bd7aaad567aa98016c26e78d8dcf by Vitaly Buka
[RISCV][ASAN] implementation of internal syscalls wrappers for riscv64

implements glibc-like wrappers over Linux syscalls.

[3/11] patch series to port ASAN for riscv64

Depends On D87998

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87572
The file was modifiedcompiler-rt/lib/sanitizer_common/CMakeLists.txt
The file was addedcompiler-rt/lib/sanitizer_common/sanitizer_syscall_linux_riscv64.inc
Commit 96034cb3d1d6d0e4ebe6848ef93707943aeca5dc by Vitaly Buka
[RISCV][ASAN] implementation of clone interceptor for riscv64

[4/11] patch series to port ASAN for riscv64

Depends On D87572

Reviewed By: eugenis, vitalybuka

Differential Revision: https://reviews.llvm.org/D87573
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.h
Commit aa1b1d35cbf60f63c7830e6711bf849902975943 by Vitaly Buka
[RISCV][ASAN] implementation for vfork interceptor for riscv64

[5/11] patch series to port ASAN for riscv64

Depends On D87573

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87574
The file was modifiedcompiler-rt/lib/asan/asan_interceptors.h
The file was modifiedcompiler-rt/lib/hwasan/hwasan_interceptors_vfork.S
The file was modifiedcompiler-rt/lib/asan/asan_interceptors_vfork.S
The file was addedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_vfork_riscv64.inc.S
Commit 00f6ebef6e347e0d24a8f940fe43656719e88cb8 by Vitaly Buka
[RISCV][ASAN] implementation of ThreadSelf  for riscv64

[6/11] patch series to port ASAN for riscv64

Depends On D87574

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87575
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit fe3c1195cfd027fdd28b6d373b3cd9519d5253ec by joker.eph
Add a dump() method on the pass manager for debugging purpose (NFC)

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D88008
The file was modifiedmlir/include/mlir/Pass/PassManager.h
The file was modifiedmlir/lib/Pass/Pass.cpp
The file was modifiedmlir/include/mlir/Pass/Pass.h
Commit f69e090d7dca6bf2786145a9e97b0a7ddb3b514a by martin
[MC] [Win64EH] Try to generate packed unwind info where possible

In practice, this only gives modest savings (for a 6.5 MB DLL with
230 KB xdata, the xdata sections shrinks by around 2.5 KB); to
gain more, the frame lowering would need to be tweaked to more often
generate frame layouts that match the canonical layouts that can
be written in packed form.

Differential Revision: https://reviews.llvm.org/D87371
The file was modifiedllvm/lib/MC/MCWin64EH.cpp
The file was addedllvm/test/MC/AArch64/seh-packed-unwind.s
The file was modifiedllvm/include/llvm/MC/MCWinEH.h
Commit 2c4c659666b400b0502e8504a708e050d0a03d6c by martin
[InstCombine] Add parentheses in assert to silence GCC warning. NFC.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
Commit b90132399aa994ac6405d0d6437735043bff9314 by martin
[CVP] Remove a redundant trailing semicolon, fixing GCC warnings. NFC.
The file was modifiedllvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
Commit d7eb917a7cb793f49e16841fc24826b988dd5c8f by albionapc
[PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

This patch implements 128-bit Binary Vector Mod and Sign Extend builtins for PowerPC10.

Differential: https://reviews.llvm.org/D87394#inline-815858
The file was modifiedclang/test/CodeGen/builtins-ppc-p9vector.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-modulo.ll
The file was addedllvm/test/CodeGen/PowerPC/p9-vector-sign-extend.ll
The file was addedllvm/test/CodeGen/PowerPC/p10-vector-sign-extend.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
Commit 1fbb5969424493344f1159d53bda5a640e3b27ae by Vitaly Buka
Revert "[RISCV][ASAN] implementation of ThreadSelf  for riscv64"

Merged two unrelated commits

This reverts commit 00f6ebef6e347e0d24a8f940fe43656719e88cb8.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit d721a2bc335ad01ff6b3838bc4759cfc35b6c8fa by Vitaly Buka
[NFC] Reformat preprocessor directives
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit 809a42e3d53518b824aad28882f9f9397f25b5b3 by Vitaly Buka
[RISCV][ASAN] implementation of ThreadSelf  for riscv64

[6/11] patch series to port ASAN for riscv64

Depends On D87574

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87575
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit b62f9f4407a5ed6e5722e177e906efcebebce9eb by ravishankarm
[mlir][Linalg] Add pattern to fold linalg.tensor_reshape that add unit extent dims.

A sequence of two reshapes such that one of them is just adding unit
extent dims can be folded to a single reshape.

Differential Revision: https://reviews.llvm.org/D88057
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
Commit 8d7fd73c3a8ce069cfe48dfcf949b4a59c05c673 by Piotr Sobczak
[AMDGPU] Fix merging m0 inits

Fix incorrect merges of m0 inits in loops.

It was assumed that if a clobbering instruction appears in
the same block as an init and the clobbering instruction
does not dominate the init then it does not interfere with
init.

This does not work in the presence of loops, where in this
scenario, the clobbering instruction does interfere with
the init in another iteration.

To fix this, do not check for block equality and defer the
decision to the predecessor check.

Differential Revision: https://reviews.llvm.org/D87882
The file was modifiedllvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-m0.mir
Commit 59c4d5aad060927fa95b917c11aad4e310849a4b by david.sherwood
[SVE] Fix InstCombinerImpl::PromoteCastOfAllocation for scalable vectors

In this patch I've fixed some warnings that arose from the implicit
cast of TypeSize -> uint64_t. I tried writing a variety of different
cases to show how this optimisation might work for scalable vectors
and found:

1. The optimisation does not work for cases where the cast type
is scalable and the allocated type is not. This because we need to
know how many times the cast type fits into the allocated type.
2. If we pass all the various checks for the case when the allocated
type is scalable and the cast type is not, then when creating the
new alloca we have to take vscale into account. This leads to
sub-optimal IR that is worse than the original IR.
3. For the remaining case when both the alloca and cast types are
scalable it is hard to find examples where the optimisation would
kick in, except for simple bitcasts, because we typically fail the
ABI alignment checks.

For now I've changed the code to bail out if only one of the alloca
and cast types is scalable. This means we continue to support the
existing cases where both types are fixed, and also the specific case
when both types are scalable with the same size and alignment, for
example a simple bitcast of an alloca to another type.

I've added tests that show we don't attempt to promote the alloca,
except for simple bitcasts:

  Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll

Differential revision: https://reviews.llvm.org/D87378
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
The file was addedllvm/test/Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll
Commit e46c1def523323eedfad1174fd2fabbece8f40cc by Raphael Isemann
Revert "[libc++] Implement LWG1203"

This reverts commit fdc41e11f9687a50c97e2a59663bf2d541ff5489. It causes the
libcxx/modules/stds_include.sh.cpp test to fail with:
libcxx/include/ostream:1039:45: error: no template named 'enable_if_t'; did you mean 'enable_if'?
template <class _Stream, class _Tp, class = enable_if_t<

Still investigating what's causing this and reverting in the meantime to get
the bots green again.
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/rvalue.pass.cpp
The file was modifiedlibcxx/include/istream
The file was modifiedlibcxx/include/ostream
The file was removedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/not_istreamable.verify.cpp
The file was removedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/rvalue.pass.cpp
The file was addedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/CharT_pointer.pass.cpp
The file was removedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/not_ostreamable.verify.cpp
The file was modifiedlibcxx/www/cxx2a_status.html
Commit e077367a28102128483f4b2555d2ad31e21b1965 by david.sherwood
[SVE] Make EVT::getScalarSizeInBits and others consistent with Type::getScalarSizeInBits

An existing function Type::getScalarSizeInBits returns a uint64_t
instead of a TypeSize class because the caller is requesting a
scalar size, which cannot be scalable. This patch makes other
similar functions requesting a scalar size consistent with that,
thereby eliminating more than 1000 implicit TypeSize -> uint64_t
casts.

Differential revision: https://reviews.llvm.org/D87889
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit d63a945a13048b66f06e222d8b0810d7db9592f6 by gabor.marton
[analyzer][StdLibraryFunctionsChecker] Fix getline/getdelim signatures

It is no longer needed to add summaries of 'getline' for different
possible underlying types of ssize_t. We can just simply lookup the
type.

Differential Revision: https://reviews.llvm.org/D88092
The file was modifiedclang/test/Analysis/std-c-library-functions.c
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
Commit 11d2e63ab0060c656398afd8ea26760031a9fb96 by gabor.marton
[analyzer][StdLibraryFunctionsChecker] Separate the signature from the summaries

The signature should not be part of the summaries as many FIXME comments
suggests. By separating the signature, we open up the way to a generic
matching implementation which could be used later under the hoods of
CallDescriptionMap.

Differential Revision: https://reviews.llvm.org/D88100
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
Commit 310af42ed9ab259ad05ed46d459203b3473ba66e by grimar
[llvm-readelf/obj] - Cleanup the code. NFCI.

This:
1) Replaces pointers with references in many places.
2) Adds few TODOs about fixing possible unhandled errors (in ARMEHABIPrinter.h).
3) Replaces `auto`s with actual types.
4) Removes excessive arguments.
5) Adds `const ELFFile<ELFT> &Obj;` member to `ELFDumper` to simplify the code.

Differential revision: https://reviews.llvm.org/D88097
The file was modifiedllvm/tools/llvm-readobj/llvm-readobj.cpp
The file was modifiedllvm/tools/llvm-readobj/ARMEHABIPrinter.h
The file was modifiedllvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.cpp
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.h
Commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6 by sebastian.neubauer
[AMDGPU] Insert waitcnt after returning from call

When memory operations are outstanding on function calls, either the
caller or the callee can insert a waitcnt to ensure that all reads are
finished.
Calls need some time to be executed, so if the callee inserts the
waitcnt, filling the instruction buffer and waiting for memory will be
interleaved, hiding some latency. This comes at the cost of having a
waitcnt inside functions that may not be needed as no memory operations
are outstanding.

For function calls, this is already implemented. The same principal
applies to returns: If the caller inserts a waitcnt after the call, the
callee does not have to wait and the return and memory operation can be
run in parallel.

This commit implements waiting in the caller after returning from a
function call.

Differential Revision: https://reviews.llvm.org/D87674
The file was modifiedllvm/test/CodeGen/AMDGPU/function-args.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr-load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory_clause.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/function-returns.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sibling-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_load_local.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-hi16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/smrd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-realign.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/hsa-func.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ret_jump.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/infer-uniform-load-shader.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_store_local.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-argument-types.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmin.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/offset-split-global.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/offset-split-flat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/nested-calls.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-waitcnt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-hi16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/imm16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/visit-physreg-vgpr-imm-folding-bug.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmax.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-lo16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
Commit d4035af2537432da41b2728829f8cd2fca9a9de8 by grimar
[llvm-readelf/obj] - Print section symbol names properly when dumping relocations.

Currently `--relocations` ignores section symbol names and always prints
section names for them. This is inconsistent with GNU readelf and with `--symbols`.

We have a code in `getFullSymbolName` (which is used for `--symbols`) which can be
reused for `getRelocationTarget` (used for `--relocations`).
With that the issue described is fixed and code becomes a bit shorter.
Also with this change we start to print more relocations (in situations when we just
showed warnings instead before) and also start to report more diagnostic warnings
(see reloc-zero-name-or-value.test).

Differential revision: https://reviews.llvm.org/D87613
The file was modifiedllvm/test/tools/llvm-readobj/ELF/section-symbols.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/relocation-errors.test
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/Inputs/compress-debug-sections.yaml
The file was modifiedllvm/test/tools/llvm-readobj/ELF/reloc-zero-name-or-value.test
Commit bd99fb4e0b5f2f3dcd8c9b81b30b4faebb765001 by grimar
[llvm-readelf/obj] - Fix extended section symbol indices printed in warnings for MIPS GOT/PLT entries.

Recent refactoring introduced a symbol index argument for `getFullSymbolName` method,
which is only used for reporting error messages about invalid extended symbol indexes.

There are few issues in the implementation and we don't report correct symbol indices
when dumping MIPS GOT/PLT entries currently.

This patch adds test cases and fixes the issue.

Differential revision: https://reviews.llvm.org/D88089
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-got.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-plt.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit d0149ba9b46d6ca08b29c9a820b5cb772c799211 by kerry.mclaughlin
[SVE][CodeGen] Lower legal integer -> floating point conversions

This patch adds new ISD nodes, SCVTZ_MERGE_PASSTHRU &
UCVTZ_MERGE_PASSTHRU, which are used to lower both legal
scalable vector [S|U]INT_TO_FP operations and the following intrinsics:
- llvm.aarch64.sve.scvtf
- llvm.aarch64.sve.ucvtf

Reviewed By: sdesmalen, efriedma

Differential Revision: https://reviews.llvm.org/D87913
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-fcvt.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit bd72ed93d22a1579362859e64a0c7f9c68460cf8 by jperier
[flang] CHARACTER(*) return does not require explicit interface

Fortran 2018 15.4.2.2(4)(c) says nonassumed or explicit non-constant
length parameter require explicit interface. The "nonassumed" part was
missing in f18 characteristic analysis causing CanBeCalledViaImplicitInterface
to return false for `CHARACTER(*) function foo()` like interfaces.

Reviewed By: klausler

Differential Revision: https://reviews.llvm.org/D88075
The file was modifiedflang/lib/Evaluate/characteristics.cpp
Commit 301e23305d03cfb4004f845a1d9dfdc5e5931fd8 by Yaxun.Liu
[CUDA][HIP] Fix static device var used by host code only

A static device variable may be accessed in host code through
cudaMemCpyFromSymbol etc. Currently clang does not
emit the static device variable if it is only referenced by
host code, which causes host code to fail at run time.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D88115
The file was modifiedclang/test/CodeGenCUDA/static-device-var-no-rdc.cu
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
Commit 34b08487f04a5a6621d94c17ef49e631cc187f4e by SourabhSingh.Tomar
[OpenMP][flang]Lower NUM_THREADS clause for parallel construct

This patch reflects the work that can be upstreamed from PR(merged)
PR: https://github.com/flang-compiler/f18-llvm-project/pull/411

Reviewed By: jeanPerier

Differential Revision: https://reviews.llvm.org/D87846
The file was modifiedflang/lib/Lower/OpenMP.cpp
Commit 5711eaf608addccc5a23f0ea00630aa30280ea13 by limo
[mlir] Added support for f64 memref printing in runner utils

Added print_memref_f64 function to runner utils.

Differential Revision: https://reviews.llvm.org/D88143
The file was modifiedmlir/lib/ExecutionEngine/RunnerUtils.cpp
The file was modifiedmlir/include/mlir/ExecutionEngine/RunnerUtils.h
Commit be1197c403b22291e35cbc5e96788860ceabd40c by SourabhSingh.Tomar
[flang] Removed OpenMP lowering unittests

These tests aren't adding much value and consensus has been reached for
there removal.
For more context, please refer to discussion in this revision:
https://reviews.llvm.org/D87846
The file was removedflang/unittests/Lower/CMakeLists.txt
The file was removedflang/unittests/Lower/OpenMPLoweringTest.cpp
The file was modifiedflang/unittests/CMakeLists.txt
Commit dfa9065ad778fe830245e627c7fd9e39f2045bc9 by SourabhSingh.Tomar
[NFCI][flang] Renamed a variable name to a more descriptive name
The file was modifiedflang/lib/Lower/OpenMP.cpp
Commit c90dee1e90045feb039be640864f038eebd1d8cd by Louis Dionne
[libc++] Re-apply fdc41e11f (LWG1203) without breaking the C++11 build

fdc41e11f was reverted in e46c1def5 because it broke the C++11 build.
We shouldn't be using enable_if_t in C++11, instead we must use
enable_if<...>::type.
The file was addedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/rvalue.pass.cpp
The file was modifiedlibcxx/www/cxx2a_status.html
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/rvalue.pass.cpp
The file was modifiedlibcxx/include/ostream
The file was addedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/not_ostreamable.verify.cpp
The file was modifiedlibcxx/include/istream
The file was addedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/not_istreamable.verify.cpp
The file was removedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/CharT_pointer.pass.cpp
Commit 20f84257ac4ac54ceb5f581a6081fac6eff2a5a1 by jotrem
[lldb] Fix GetRemoteSharedModule fallback logic

When the various methods of locating the module in GetRemoteSharedModule
fail, make sure we pass the original module spec to the bail-out call to
the provided resolver function.

Also make sure we consistently use the resolved module spec from the
various success paths.

Thanks to what appears to have been an accidentally inverted condition
(commit 85967fa applied the new condition to a path where GetModuleSpec
returns false, but should have applied it when GetModuleSpec returns
true), without this fix we only pass the original module spec in the
fallback if the original spec has no uuid (or has a uuid that somehow
matches the resolved module's uuid despite the call to GetModuleSpec
failing).  This manifested as a bug when processing a minidump file with
a user-provided sysroot, since in that case the resolver call was being
applied to resolved_module_spec (despite resolution failing), which did
not have the path of its file_spec set.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D88099
The file was modifiedlldb/test/API/functionalities/postmortem/minidump-new/TestMiniDumpNew.py
The file was modifiedlldb/source/Target/Platform.cpp
Commit af0207f2bae8578c5283877a786e502ce6e33b14 by Matthew.Arsenault
AMDGPU: Check global FP atomics match default FP mode

We would always select global FP atomics from atomicrmw fadd, although
they have a hardcoded FP mode.
The file was modifiedllvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit c463fd136ec259ec269ee6741763ce595811da71 by Matthew.Arsenault
GlobalISel: Fix truncating shift amount in trunc (shl) combine

The shift amount type does not necessarily match the result type. This
was inserting a trunc from s32 to s32, which asserted. Just preserve
the original shift amount type which can be legalized later.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shl.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Commit 1d1c382ed221f378fc866a524c7c673c239e94bc by aaron
Fix typos in ASTMatchers.h; NFC
The file was modifiedclang/docs/LibASTMatchersReference.html
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
Commit 00c34f72fba4b6b8a446d57e2257c27eedad1a1d by sam.parker
[NFC][ARM] Pre-commit tail predication test
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
Commit 370a8c802558ed7aedbcc09c1bdf4c2d3f4c28c0 by paulsson
[SystemZ] Make sure not to call getZExtValue on a >64 bit constant.

Better use isZero() and isIntN() in SystemZTargetTransformInfo rather than
calling getZExtValue() since the immediate operand may be wider than 64 bits,
which is not allowed with getZExtValue().

Fixes https://bugs.llvm.org/show_bug.cgi?id=47600

Review: Simon Pilgrim
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
The file was addedllvm/test/Analysis/CostModel/SystemZ/huge-immediates.ll
Commit 9691806840606d48139b13516e9576902ba98923 by zinenko
[mlir] Fix typos in Dialect.h. NFC.
The file was modifiedmlir/include/mlir/IR/Dialect.h
Commit 31923f6b360300b8b148ad257419766999dfe504 by flo
[VPlan] Disconnect VPValue and VPUser.

This refactors VPuser to not inherit from VPValue to facilitate
introducing operations that introduce multiple VPValues (e.g.
VPInterleaveRecipe).

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D84679
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/docs/Proposals/VectorizationPlan.rst
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanSLP.cpp
Commit db40a74344292410aa3e08c42834423013c4f192 by mcinally
[SVE] Lower fixed length ISD::VECREDUCE_ADD to Scalable

Differential Revision: https://reviews.llvm.org/D87796
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 158af0d3d165c0382a6a291e81ffecf0b18ffe77 by usx
[clangd] Refactor code completion signal's utility properties.

Current implementation of heuristic-based scoring function also contains
computation of derived signals (e.g. whether name contains a word from
context, computing file distances, scope distances.)
This is an attempt to separate out the logic for computation of derived
signals from the scoring function.
This will allow us to have a clean API for scoring functions that will
take only concrete code completion signals as input.

Differential Revision: https://reviews.llvm.org/D88146
The file was modifiedclang-tools-extra/clangd/Quality.h
The file was modifiedclang-tools-extra/clangd/Quality.cpp
Commit 270d334a665faa574db0c7d3a23af78bed9366d0 by paul
[docs][llvm] Fix typos

I don't have commit access.
Please help me commit it.
Thanks : )

Reviewed By: Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D88139
The file was modifiedllvm/docs/TableGen/BackGuide.rst
Commit bd8b50cd7f5dd5237ec9187ef2fcea3adc15b61a by clementval
[mlir][openacc] Use OptionalParseResult in loop op parser instead of bool variables

This patch switch from using bool variables to OptionalParseResult for the parsing
inside loop operation. This is already done for parallel operation and this patch unify this
in the dialect.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D88111
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp