SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. Fix sphinx warnings in AttributeReference, NFC (details)
  2. [NFC][PowerPC] Change PPCSubTarget (introduced from D87671) to Subtarget (details)
  3. Internalize functions from various tools. NFC (details)
  4. [LLVM-C] Turn a ShuffleVector Constant Into a Getter. (details)
  5. [Machinesink] add one more profitable loop related pattern (details)
  6. Update Kaleidoscope: Change headers (details)
  7. [X86] Add more test cases to inline-asm-flag-output.ll. NFC (details)
  8. [DivRemPairs] Use DenseMapBase::find instead of operator[]. NFC (details)
  9. [AArch64][GlobalISel] Use the look-through constant helper for the shift s32->s64 custom legalization. (details)
  10. [Legalize][X86] Improve nnan fmin/fmax vector reduction (details)
  11. [AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64. (details)
Commit 485501899d6c752ff05f4e045f7f89ace39ec413 by aaronpuchert
Fix sphinx warnings in AttributeReference, NFC

The previous attempt in d34c8c70 didn't help (the problem was missing
indentation), and another issue was introduced by a51d51a0.
The file was modifiedclang/include/clang/Basic/AttrDocs.td
Commit 6f24774fc4e296b9047e5873c070af4e0fd638e5 by amy.kwan1
[NFC][PowerPC] Change PPCSubTarget (introduced from D87671) to Subtarget

In D87671, it introduced PPCSubTarget in PPCISelDAGToDAG. This should have been
Subtarget instead. This patch changes PPCSubTarget into Subtarget.
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Commit 20e9c36c013c4a9b13cf256ca5262afe3def78ad by i
Internalize functions from various tools. NFC

And internalize some classes if I noticed them:)
The file was modifiedllvm/tools/llvm-cvtres/llvm-cvtres.cpp
The file was modifiedllvm/tools/llvm-mt/llvm-mt.cpp
The file was modifiedllvm/tools/llvm-cfi-verify/llvm-cfi-verify.cpp
The file was modifiedllvm/utils/TableGen/SubtargetEmitter.cpp
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedllvm/tools/llvm-ar/llvm-ar.cpp
The file was modifiedllvm/tools/llvm-ifs/llvm-ifs.cpp
The file was modifiedllvm/tools/llvm-xray/xray-stacks.cpp
The file was modifiedllvm/tools/sanstats/sanstats.cpp
The file was modifiedllvm/tools/llvm-jitlink/llvm-jitlink.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
The file was modifiedllvm/tools/opt/opt.cpp
The file was modifiedllvm/tools/llvm-lto/llvm-lto.cpp
The file was modifiedllvm/utils/TableGen/RegisterInfoEmitter.cpp
The file was modifiedllvm/tools/llvm-dwp/llvm-dwp.cpp
The file was modifiedllvm/utils/FileCheck/FileCheck.cpp
Commit 55f727306e727ea9f013d09c9b8aa70dbce6a1bd by devteam.codafi
[LLVM-C] Turn a ShuffleVector Constant Into a Getter.

It is not a good idea to expose raw constants in the LLVM C API. Replace this with an explicit getter.

Differential Revision: https://reviews.llvm.org/D88367
The file was modifiedllvm/lib/IR/Core.cpp
The file was modifiedllvm/include/llvm-c/Core.h
The file was modifiedllvm/tools/llvm-c-test/echo.cpp
Commit c8f6c0f961eed1301b33b8af53d075542f7723c8 by czhengsz
[Machinesink] add one more profitable loop related pattern

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D86925
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
The file was removedllvm/test/CodeGen/PowerPC/sink-down-more-instructions.ll
Commit ba950ad0a51066868fbca37a8ad244eac9a228b7 by llvm
Update Kaleidoscope: Change headers

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D88141
The file was modifiedllvm/examples/Kaleidoscope/Chapter2/toy.cpp
Commit d78c4d9d00c15c52f0463c8dbb03945b036d53eb by craig.topper
[X86] Add more test cases to inline-asm-flag-output.ll. NFC

These are tests to make sure we are able to use the flag directly
in a conditional branch after the inline asm.
The file was modifiedllvm/test/CodeGen/X86/inline-asm-flag-output.ll
Commit 82420b4e49ff92c49c2b548bf541a5655e97d197 by i
[DivRemPairs] Use DenseMapBase::find instead of operator[]. NFC
The file was modifiedllvm/lib/Transforms/Scalar/DivRemPairs.cpp
Commit 7156938be26405156e17aa29e1c04e1afde88b04 by Amara Emerson
[AArch64][GlobalISel] Use the look-through constant helper for the shift s32->s64 custom legalization.

Almost NFC, except it catches more cases and gives a 0.1% CTMark -O0 size win.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
Commit f229bf2e12461be55446e6b08ccb931308586031 by nikita.ppv
[Legalize][X86] Improve nnan fmin/fmax vector reduction

Use +/-Inf or +/-Largest as neutral element for nnan fmin/fmax
reductions. This avoids dropping any FMF flags. Preserving the
nnan flag in particular is important to get a good lowering on X86.

Differential Revision: https://reviews.llvm.org/D87586
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Commit 5811d723998a3abdd3cb95dc579d28f48c57c2fa by Amara Emerson
[AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64.

This was supposed to be done in the first place as is currently the case for
G_ASHR and G_LSHR but was forgotten when the original shift legalization
overhaul was done last year.

This was exposed because we started falling back on s32 = s32, s64 SHLs
due to a recent combiner change.

Gives a very minor (0.1%) code size -O0 improvement on consumer-typeset.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
The file was modifiedllvm/test/CodeGen/AArch64/arm64-clrsb.ll