SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. [zorg] [PowerPC] Limit number of threads to 64 on clang-ppc64le-rhel buildbot (details)
Commit c2cc01b14ef84bee845318bde3ae623091934b96 by saghir
[zorg] [PowerPC] Limit number of threads to 64 on clang-ppc64le-rhel buildbot

This patch reduces the number of threads from 256 to 64 on the
clang-ppc64le-rhel buildbot.

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D88586
The file was modifiedbuildbot/osuosl/master/config/builders.py

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [docs] Recommend dropLocation() over setDebugLoc(DebugLoc()) (details)
  2. [NFC][MSAN] Remove an attribute in test (details)
  3. [NFC][Msan] Add llvm.fabs test (details)
  4. Fix test failures with trunk clang (details)
  5. [lldb] Hoist -s (trace directory) argument out of LLDB_TEST_COMMON_ARGS (NFC) (details)
  6. [gardening] Replace some uses of setDebugLoc(DebugLoc()) with dropLocation(), NFC (details)
  7. Add remquo, frexp and modf overload functions to HIP header (details)
  8. [RISCV] Use the extensions in the canonical order (NFC) (details)
  9. [AIX] asm output: use character literals in byte lists for strings (details)
  10. [X86] Increase the depth threshold required to form VPERMI2W/VPERMI2B in shuffle combining (details)
  11. [GlobalISel] Fix multiply with overflow intrinsics legalization generating invalid MIR. (details)
  12. Remove further OpenBSD/sparc bits (details)
  13. [gn build] Add missing dependency to Extensions (details)
  14. [mlir] Update docs referencing OpTrait::Symbol. (details)
  15. Remove test AST/const-fpfeatures-diag.c (details)
  16. [lldb] Use config.lldb_src_root in lit_config.load_config (NFC) (details)
  17. [ARM] Change VPT state assertion (details)
  18. [RDA] Switch isSafeToMove iterators (details)
  19. [NFC][ARM] Add LowOverheadLoop test (details)
  20. [clangd] Extract options struct for ClangdLSPServer. NFC (details)
  21. [clangd] Mark code action as "preferred" if it's the sole quickfix action (details)
  22. [ARM][LowOverheadLoops] TryRemove helper. (details)
  23. [MLIR][Standard] Add `atan2` to standard dialect (details)
  24. [llvm-readobj][ARM] - Improve support of printing unwind (-u) information for non-relocatable objects. (details)
  25. [llvm-readobj][test] - Stop using few precompiled binaries in mips-got.test (details)
  26. Revert "[gardening] Replace some uses of setDebugLoc(DebugLoc()) with dropLocation(), NFC" (details)
  27. [clangd] Fix member/type name conflict caught by buildbots. (details)
  28. [clangd] Fix fuzzer build after 7ba0779fbb41b6fa8 (details)
  29. [clangd][remote] Make sure relative paths are absolute with respect to posix style (details)
  30. [AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer (details)
  31. [SplitKit] Cope with no live subranges in defFromParent (details)
  32. [SystemZ]  Support bare nop instructions (details)
  33. [MLIR][SPIRV] Support different function control in (de)serialization (details)
  34. [X86] Support Intel Key Locker (details)
  35. [gn build] Port 413577a8790 (details)
  36. [InstCombine] recognizeBSwapOrBitReverseIdiom - assert for correct bit providence indices. NFCI. (details)
  37. [InstCombine] recognizeBSwapOrBitReverseIdiom - recognise zext(bswap(trunc(x))) patterns (PR39793) (details)
  38. [mlir] Added support for rank reducing subviews (details)
  39. [NFC][ARM] Add more LowOverheadLoop tests. (details)
  40. [mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments (details)
  41. [SCEV] Verify that all mapped SCEV AddRecs refer to valid loops. (details)
  42. InstCombine] collectBitParts - cleanup variable names. NFCI. (details)
  43. [InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI. (details)
  44. [RDA] isSafeToDefRegAt: Look at global uses (details)
  45. [InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI. (details)
  46. [InstCombine] Add PR47191 bswap tests (details)
  47. [lldb] Fix FreeBSD Arm Process Plugin build (details)
  48. [VPlan] Change recipes to inherit from VPUser instead of a member var. (details)
  49. [lldb] [Process/NetBSD] Fix operating on ftag register (details)
  50. [InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI. (details)
  51. [InstCombine] Remove %tmp variable names from bswap tests (details)
  52. [InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI. (details)
  53. [clangd] Fix invalid UTF8 when extracting doc comments. (details)
  54. [PowerPC] Remove support for VRSAVE save/restore/update. (details)
  55. [GlobalISel] Fix incorrect setting of ValNo when splitting (details)
  56. Move AffineMapAttr into BaseOps.td (details)
  57. [sanitizers] Fix internal__exit on Solaris (details)
  58. [NFC][FE] Replace TypeSize with StorageUnitSize (details)
  59. Reapply "RegAllocFast: Rewrite and improve" (details)
  60. RegAllocFast: Add extra DBG_VALUE for live out spills (details)
  61. LiveDebugValues: Fix typos and indentation (details)
  62. GlobalISel: Assert if MoreElements uses a non-vector type (details)
  63. [InstCombine] Remove %tmp variable names from bswap-fold tests (details)
  64. [FE] Use preferred alignment instead of ABI alignment for complete object when applicable (details)
  65. [mlir][Linalg] Generalize the logic to compute reassociation maps (details)
  66. [InstCombine] Add bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector tests (details)
  67. [InstCombine] Fix bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector support (details)
  68. [PowerPC] Avoid unused variable warning in Release builds (details)
  69. [PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9 (details)
  70. [InstCombine] Add tests for 'partial' bswap patterns (details)
  71. [NFC][regalloc] Make VirtRegAuxInfo part of allocator state (details)
  72. [DA][SDA] SyncDependenceAnalysis re-write (details)
  73. [VE] Support TargetBlockAddress (details)
  74. [ObjCARCAA][NewPM] Add already ported objc-arc-aa to PassRegistry.def (details)
  75. [mlir][openacc] Remove -allow-unregistred-dialect from ops and invalid tests (details)
  76. [llvm-exegesis] Add option to check the hardware support for a given feature before benchmarking. (details)
Commit f71849c74ed58e5d9ed3681cc6294128098012dc by Vedant Kumar
[docs] Recommend dropLocation() over setDebugLoc(DebugLoc())
The file was modifiedllvm/docs/HowToUpdateDebugInfo.rst
Commit 616c68aab75016d5d7ebc0b79bb3c38405b18ae6 by Vitaly Buka
[NFC][MSAN] Remove an attribute in test
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/abs-vector.ll
Commit 795d94fdb9d2377452f86952dcf0921a6c68d2b5 by Vitaly Buka
[NFC][Msan] Add llvm.fabs test

llvm.fabs does not need a special handler as llvm.abs as its
single argument type match the return type.
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/abs-vector.ll
Commit afcf9c47c5e74a0b567531547b677ff1d383ae50 by richard
Fix test failures with trunk clang

- Make the consteval constructor for the zero type be noexcept
- Don't expect three-way comparison of 0 against a comparison category
  to fail
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.categories.pre/zero_type.verify.cpp
The file was modifiedlibcxx/include/compare
Commit bd14d6ea1517c93ceecaec29dad016d9a122fa1b by Jonas Devlieghere
[lldb] Hoist -s (trace directory) argument out of LLDB_TEST_COMMON_ARGS (NFC)

Give the trace directory argument its own variable
(LLDB_TEST_TRACE_DIRECTORY) so that we can configure it in
lit.site.cfg.py if we so desire.
The file was modifiedlldb/test/API/lit.cfg.py
The file was modifiedlldb/test/API/lit.site.cfg.py.in
The file was modifiedlldb/utils/lldb-dotest/CMakeLists.txt
The file was modifiedlldb/utils/lldb-dotest/lldb-dotest.in
The file was modifiedlldb/test/API/CMakeLists.txt
Commit 674f57870f4c8a7fd7b629bffc85b149cbefd3e0 by Vedant Kumar
[gardening] Replace some uses of setDebugLoc(DebugLoc()) with dropLocation(), NFC
The file was modifiedllvm/lib/Transforms/Scalar/LICM.cpp
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit d04775e16bba456f0be0aaa7478959c5bfa22c41 by Yaxun.Liu
Add remquo, frexp and modf overload functions to HIP header
The file was modifiedclang/lib/Headers/__clang_hip_math.h
Commit c6b18cf9672bca4f61bb3ef401173742068e46ea by ebahapo
[RISCV] Use the extensions in the canonical order (NFC)

Use the ISA extensions for specific processors in the conventional canonical order.
The file was modifiedllvm/lib/Target/RISCV/RISCV.td
Commit 0a146a9d0bdd54411f0b0712e27481a4c280ae03 by hubert.reinterpretcast
[AIX] asm output: use character literals in byte lists for strings

This patch improves the assembly output produced for string literals by
using character literals in byte lists. This provides the benefits of
having printable characters appear as such in the assembly output and of
having strings kept as logical units on the same line.

Reviewed By: daltenty

Differential Revision: https://reviews.llvm.org/D80953
The file was addedllvm/test/CodeGen/PowerPC/aix-bytestring.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
The file was modifiedllvm/lib/MC/MCAsmStreamer.cpp
The file was modifiedllvm/include/llvm/MC/MCAsmInfo.h
The file was modifiedllvm/lib/MC/MCAsmInfoXCOFF.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll
Commit 618a890b72f874cbc41168737d03f724f58805fc by craig.topper
[X86] Increase the depth threshold required to form VPERMI2W/VPERMI2B in shuffle combining

These instructions are implemented with two port 5 uops and one port 015 uop so they are more complicated that most shuffles.

This patch increases the depth threshold for when we form them during shuffle combining to try to limit increasing the number of uops especially on port 5.

Differential Revision: https://reviews.llvm.org/D88503
The file was modifiedllvm/test/CodeGen/X86/min-legal-vector-width.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-zext.ll
Commit 1d54e75cf26a4c60b66659d5d9c62f4bb9452b03 by Amara Emerson
[GlobalISel] Fix multiply with overflow intrinsics legalization generating invalid MIR.

During lowering of G_UMULO and friends, the previous code moved the builder's
insertion point to be after the legalizing instruction. When that happened, if
there happened to be a "G_CONSTANT i32 0" immediately after, the CSEMIRBuilder
would try to find that constant during the buildConstant(zero) call, and since
it dominates itself would return the iterator unchanged, even though the def
of the constant was *after* the current insertion point. This resulted in the
compare being generated *before* the constant which it was using.

There's no need to modify the insertion point before building the mul-hi or
constant. Delaying moving the insert point ensures those are built/CSEd before
the G_ICMP is built.

Fixes PR47679

Differential Revision: https://reviews.llvm.org/D88514
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
Commit 6f01c53f26af7fb0393464079ec5e839a497d4da by brad
Remove further OpenBSD/sparc bits
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp
Commit e6e73712ddfa18d4a2937a5775990dcefc8bd2f7 by aeubanks
[gn build] Add missing dependency to Extensions
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Extensions/BUILD.gn
Commit 1c5aa8aeca29c7d4b891e5b60b25fdb74f9bf0e9 by joker.eph
[mlir] Update docs referencing OpTrait::Symbol.

Since https://reviews.llvm.org/D78522, Symbol is not a Trait itself.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D88512
The file was modifiedmlir/docs/Traits.md
The file was modifiedmlir/docs/SymbolsAndSymbolTables.md
The file was modifiedmlir/docs/Interfaces.md
Commit 4e4f926e83cf77f0d36b821a3d2aa1de78338a82 by sepavloff
Remove test AST/const-fpfeatures-diag.c

This test is going to be removed because using dynamic rounding mode
in initializers is changing. It also causes build failures in some
cases, so remove it now.
The file was removedclang/test/AST/const-fpfeatures-diag.c
Commit 154860af338f7b0c82cb04e91d6f199aa72cfdff by Jonas Devlieghere
[lldb] Use config.lldb_src_root in lit_config.load_config (NFC)

Rather than relaying on CMake to substitute the full path to the lldb
source root, use the  value set in config.lldb_src_root. This makes it
slightly easier to write a custom lit.site.cfg.py.
The file was modifiedlldb/test/API/lit.site.cfg.py.in
The file was modifiedlldb/test/Unit/lit.site.cfg.py.in
The file was modifiedlldb/test/Shell/lit.site.cfg.py.in
Commit 195c22f2733cf923b932412f0fe212f4ef397d2c by sam.parker
[ARM] Change VPT state assertion

Just because we haven't encountered an instruction setting the VPR,
it doesn't mean we can't create a VPT block - the VPR maybe a
live-in.

Differential Revision: https://reviews.llvm.org/D88224
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/begin-vpt-without-inst.mir
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Commit 700f93e92b6d4cdbab66133f75c143c9677f2d41 by sam.parker
[RDA] Switch isSafeToMove iterators

So forwards is forwards and backwards is reverse. Also add a check
so that we know the instructions are in the expected order.

Differential Revision: https://reviews.llvm.org/D88419
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
Commit 834b6470d9f111c355053ecff8bed71bf44a6624 by sam.parker
[NFC][ARM] Add LowOverheadLoop test
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir
Commit 7ba0779fbb41b6fa8213aa31622ff45484037eb4 by sam.mccall
[clangd] Extract options struct for ClangdLSPServer. NFC

In preparation for making moving TweakFilter from ClangdServer::Options to
a ClangdLSPServer option, and letting it vary per-request.
(In order to implement CodeActionParams.only)

Also a general overdue cleanup.

Differential Revision: https://reviews.llvm.org/D88470
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.h
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp
The file was modifiedclang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp
Commit 8392685c2b9f3c2025100dd25b6c6e5eae312d92 by sam.mccall
[clangd] Mark code action as "preferred" if it's the sole quickfix action

Differential Revision: https://reviews.llvm.org/D88489
The file was modifiedclang-tools-extra/clangd/Protocol.h
The file was modifiedclang-tools-extra/clangd/Protocol.cpp
The file was modifiedclang-tools-extra/clangd/test/fixits-embed-in-diagnostic.test
The file was modifiedclang-tools-extra/clangd/Diagnostics.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
Commit 779a8a028f53f16234b41e5252b805304788b989 by sam.parker
[ARM][LowOverheadLoops] TryRemove helper.

Make a helper function that wraps around RDA::isSafeToRemove and
utilises the existing DCE IT block checks.
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
Commit cdda7822d6ce9cd6fe305e6fffedf3480d4bb769 by frgossen
[MLIR][Standard] Add `atan2` to standard dialect

Differential Revision: https://reviews.llvm.org/D88168
The file was modifiedmlir/test/Dialect/Standard/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit fdceec7aeac6ae0fba4db9703bf4e4e69a126d0d by grimar
[llvm-readobj][ARM] - Improve support of printing unwind (-u) information for non-relocatable objects.

This is the one more patch for https://bugs.llvm.org/show_bug.cgi?id=47581

It fixes how we print an information for the Generic model. With this patch
we are able to read values from `.ARM.extab` and dump proper personality routines names/addresses.

Differential revision: https://reviews.llvm.org/D88478
The file was modifiedllvm/test/tools/llvm-readobj/ELF/ARM/unwind-non-relocatable.test
The file was modifiedllvm/tools/llvm-readobj/ARMEHABIPrinter.h
Commit 0767a0b53e37009a70788c2a44834ed14a951cba by grimar
[llvm-readobj][test] - Stop using few precompiled binaries in mips-got.test

This removes 4 input files (one source file and 3 precompiled binaries) from
`mips-got.test` (now YAMLs are used instead) and also makes the testing of
the GNU output a bit stricter (`--strict-whitespace --match-full-lines`).

Differential revision: https://reviews.llvm.org/D88488
The file was removedllvm/test/tools/llvm-readobj/ELF/Inputs/got-tls.so.elf-mips64el
The file was removedllvm/test/tools/llvm-readobj/ELF/Inputs/dynamic-table-so.mips
The file was removedllvm/test/tools/llvm-readobj/ELF/Inputs/dynamic-table.c
The file was removedllvm/test/tools/llvm-readobj/ELF/Inputs/dynamic-table-exe.mips
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-got.test
Commit 05659606a2af76710fb19a65fbd1a6c88ba12dad by jeremy.morse
Revert "[gardening] Replace some uses of setDebugLoc(DebugLoc()) with dropLocation(), NFC"

Some of the buildbots have croaked with this patch, for examples failures
that begin in this build:

  http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/29933

This reverts commit 674f57870f4c8a7fd7b629bffc85b149cbefd3e0.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LICM.cpp
Commit 6342b38c5fee74df94d7b0c34e5a93b9b22763df by sam.mccall
[clangd] Fix member/type name conflict caught by buildbots.
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.h
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp
Commit d99f46c6eb8debaa1a14c122956177dc2a40ef9b by sam.mccall
[clangd] Fix fuzzer build after 7ba0779fbb41b6fa8
The file was modifiedclang-tools-extra/clangd/fuzzer/clangd-fuzzer.cpp
Commit 64e8fd540ecc38ee3daf942499091589785e2733 by kadircet
[clangd][remote] Make sure relative paths are absolute with respect to posix style

Relative paths received from the server are always in posix style. So
we need to ensure they are relative using that style, and not the native one.

Differential Revision: https://reviews.llvm.org/D88507
The file was modifiedclang-tools-extra/clangd/index/remote/marshalling/Marshalling.cpp
Commit 0249df33fec16b728e2d33cae02f5da4c9f74e38 by Mirko.Brkusanin
[AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer

Check if operand of mul is constant value of one for certain atomic
instructions in order to avoid making unnecessary instructions when
-amdgpu-atomic-optimizer is present.

Differential Revision: https://reviews.llvm.org/D88315
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
Commit cdac4492b4a523a888a013d42ea0a968f684ed59 by jay.foad
[SplitKit] Cope with no live subranges in defFromParent

Following on from D87757 "[SplitKit] Only copy live lanes", it is
possible to split a live range at a point when none of its subranges
are live. This patch handles that case by inserting an implicit def
of the superreg.

Patch by Quentin Colombet!

Differential Revision: https://reviews.llvm.org/D88397
The file was addedllvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
Commit 9f5da55f5d9299a76a4dfb67ef0324dbc1900826 by paulsson
[SystemZ]  Support bare nop instructions

Add support of "nop" and "nopr" (without operands) to assembler.

Review: Ulrich Weigand
The file was modifiedllvm/test/MC/SystemZ/insn-good.s
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.td
Commit 8c05c7c8d87c7ab02fca2a789dfcca4976c6601b by georgemitenk0v
[MLIR][SPIRV] Support different function control in (de)serialization

Added support for different function control
in serialization and deserialization.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D88280
The file was modifiedmlir/test/Dialect/SPIRV/Serialization/module.mlir
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp
Commit 413577a8790407d75ba834fa5668c2632fe1851e by xiang1.zhang
[X86] Support Intel Key Locker

Key Locker provides a mechanism to encrypt and decrypt data with an AES key without having access
to the raw key value by converting AES keys into “handles”. These handles can be used to perform the
same encryption and decryption operations as the original AES keys, but they only work on the current
system and only until they are revoked. If software revokes Key Locker handles (e.g., on a reboot),
then any previous handles can no longer be used.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D88398
The file was addedllvm/lib/Target/X86/X86InstrInfo.td.rej
The file was modifiedclang/include/clang/Driver/Options.td
The file was addedllvm/lib/Target/X86/X86InstrKL.td
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-32-intel.txt
The file was modifiedclang/include/clang/Basic/BuiltinsX86.def
The file was modifiedclang/test/Driver/x86-target-features.c
The file was modifiedllvm/lib/IR/Function.cpp
The file was modifiedclang/lib/Basic/Targets/X86.h
The file was addedllvm/test/MC/X86/KEYLOCKER/x86-64-keylocker-att.s
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was addedclang/lib/Headers/keylockerintrin.h
The file was addedllvm/test/MC/X86/KEYLOCKER/keylocker-intel.s
The file was addedllvm/test/MC/X86/KEYLOCKER/keylocker-att.s
The file was modifiedllvm/include/llvm/IR/IntrinsicsX86.td
The file was modifiedclang/lib/Headers/CMakeLists.txt
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-64-intel.txt
The file was modifiedllvm/lib/Target/X86/X86.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was addedllvm/test/CodeGen/X86/keylocker-intrinsics.ll
The file was modifiedclang/lib/Basic/Targets/X86.cpp
The file was modifiedclang/test/CodeGen/attr-target-x86.c
The file was modifiedllvm/lib/Support/X86TargetParser.cpp
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-32-att.txt
The file was modifiedllvm/lib/Support/Host.cpp
The file was modifiedllvm/include/llvm/Support/X86TargetParser.def
The file was addedclang/lib/Headers/keylocker_wide_intrin.h
The file was addedllvm/test/MC/X86/KEYLOCKER/x86-64-keylocker-intel.s
The file was modifiedclang/lib/Headers/immintrin.h
The file was addedclang/test/CodeGen/X86/keylocker.c
The file was modifiedclang/test/Preprocessor/x86_target_features.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/Target/X86/X86Subtarget.h
The file was addedllvm/test/MC/Disassembler/X86/KEYLOCKER/Keylocker-x86-64-att.txt
Commit e39d7884a1f5c5c7136ba2e493e9ac313ccc78ed by llvmgnsyncbot
[gn build] Port 413577a8790
The file was modifiedllvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Commit ec3f24d4538d1c262377331c7b35ea66e023cf98 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - assert for correct bit providence indices. NFCI.

As suggested by @spatel on D88316
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit af47d40b9c68744eb66aa2ef779065e946aaa099 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - recognise zext(bswap(trunc(x))) patterns (PR39793)

PR39793 demonstrated an issue where we fail to recognize 'partial' bswap patterns of the lower bytes of an integer source.

In fact, most of this is already in place collectBitParts suitably tags zero bits, so we just need to correctly handle this case by finding the zero'd upper bits and reducing the bswap pattern just to the active demanded bits.

Differential Revision: https://reviews.llvm.org/D88316
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit 14088a6f5d1ae597960833a366beb9acee8d65cb by limo
[mlir] Added support for rank reducing subviews

This commit adds support for subviews which enable to reduce resulting rank
by dropping static dimensions of size 1.

Differential Revision: https://reviews.llvm.org/D88534
The file was modifiedmlir/test/IR/invalid-ops.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/IR/core-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit 3cbd01ddb9372b725dcea3dd5fed21ef5b3d9578 by sam.parker
[NFC][ARM] Add more LowOverheadLoop tests.
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
Commit 0b17d4754a94b7129c2483762acd586783802b12 by limo
[mlir][Linalg] Tile sizes for Conv ops vectorization added as pass arguments

Current setup for conv op vectorization does not enable user to specify tile
sizes as well as dimensions for vectorization. In this commit we change that by
adding tile sizes as pass arguments. Every dimension with corresponding tile
size > 1 is automatically vectorized.

Differential Revision: https://reviews.llvm.org/D88533
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-call.mlir
The file was modifiedmlir/test/lib/Transforms/TestConvVectorization.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ndhwc-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-ncw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ncdhw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-call.mlir
The file was modifiedmlir/test/Conversion/LinalgToVector/linalg-to-vector.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nhwc-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nchw-call.mlir
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-nwc-call.mlir
Commit 0eab9d5823815c6520697f8d725c402c88e5d050 by flo
[SCEV] Verify that all mapped SCEV AddRecs refer to valid loops.

This check helps to guard against cases where expressions referring to
invalidated/deleted loops are not properly invalidated.

The additional check is motivated by the reproducer shared for 8fdac7cb7abb
and I think in general make sense as a sanity check.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D88166
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 05290eead3f95e02700890321ccf6719770f91fe by llvm-dev
InstCombine] collectBitParts - cleanup variable names. NFCI.

Fix a number of WShadow warnings (I was used as the instruction and index......) and fix cases to match style.

Also, replaced the Bit APInt mask check in AND instructions with a direct APInt[] bit check.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 413b4998bd722ab671e29e6dff5d458d1869f39b by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - use ArrayRef::back() helper. NFCI.

Post-commit feedback on D88316
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 3f88c10a6b25668bb99f5eee7867dcbf37df973c by sam.parker
[RDA] isSafeToDefRegAt: Look at global uses

We weren't looking at global uses of a value, so we could happily
overwrite the register incorrectly.

Differential Revision: https://reviews.llvm.org/D88554
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
Commit 621c6c89627972d52796e64a9476a7d05f22f2cd by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - cleanup bswap/bitreverse detection loop. NFCI.

Early out if both pattern matches have failed (or we don't want them). Fix case of bit index iterator (and avoid Wshadow issue).
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 08c5720405d5204ec2329b7f6c561062c7dddee2 by llvm-dev
[InstCombine] Add PR47191 bswap tests
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit f794160c6cb7da4b5ef354a91fe498341f651d36 by emaste
[lldb] Fix FreeBSD Arm Process Plugin build

Add a missing include and some definitions in 769533216666.

Patch by: Brooks Davis

Reviewed by: labath

Differential Revision: https://reviews.llvm.org/D88453
The file was modifiedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.h
Commit d8563654701c79fb9ab28ecf94567d9934baed05 by flo
[VPlan] Change recipes to inherit from VPUser instead of a member var.

Now that VPUser is not inheriting from VPValue, we can take the next
step and turn the recipes that already manage their operands via VPUser
into VPUsers directly. This is another small step towards traversing
def-use chains in VPlan.

This is NFC with respect to the generated code, but makes the interface
more powerful.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
Commit 762e8f9bbdaf43300dbc75637a8bce1ce643cc06 by mgorny
[lldb] [Process/NetBSD] Fix operating on ftag register
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
Commit d5545a8993489ee426b757482a64c9373cf7cf38 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - remove unnecessary cast. NFCI.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 7fcad5583a12026ce19afe487681753ac633064a by llvm-dev
[InstCombine] Remove %tmp variable names from bswap tests

Appease update_test_checks script that was complaining about potential %TMP clashes
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit c722b3259690d3aad20f31d0ffe6c12b1416bccc by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - merge the regular/trunc+zext paths. NFCI.

There doesn't seem to be any good reason for having a separate path for when we bswap/bitreverse at a smaller size than the destination size - so merge these to make the instruction generation a lot clearer.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 216af81c39d1cc4e90af7b991d517c4c7acc912e by sam.mccall
[clangd] Fix invalid UTF8 when extracting doc comments.

Differential Revision: https://reviews.llvm.org/D88567
The file was modifiedclang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CodeCompletionStringsTests.cpp
The file was modifiedclang-tools-extra/clangd/CodeCompletionStrings.cpp
Commit dfb717da1f794c235b81a985a57dc238c82318e6 by sd.fertile
[PowerPC] Remove support for VRSAVE save/restore/update.

After removal of Darwin as a PowerPC subtarget, the VRSAVE
save/restore/spill/update code is no longer needed by any supported
subtarget, so remove it while keeping support for vrsave and related instruction
aliases for inline asm. I've pre-commited tests to document the existing vrsave
handling in relation to @llvm.eh.unwind.init and inline asm usage, as
well as a test which shows a beahviour change on AIX related to
returning vector type as we were wrongly emiting VRSAVE_UPDATE on AIX.
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/aix-vector-return.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.h
The file was modifiedllvm/lib/Target/PowerPC/README_ALTIVEC.txt
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Commit 43d239d0fadb1f8ea297580ca39dfbee96c913c1 by mikael.holmen
[GlobalISel] Fix incorrect setting of ValNo when splitting

Before, for each original argument i, ValNo was set to i + PartIdx, but
ValNo is intended to reflect the index of the value before splitting.
Hence, ValNo should always be set to i and not consider the PartIdx.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D86511
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit f33f8a2b30325d89c4b7daef1b7d11d6da38fd56 by benny.kra
Move AffineMapAttr into BaseOps.td

AffineMapAttr is already part of base, it's just impossible to refer to
it from ODS without pulling in the definition from Affine dialect.

Differential Revision: https://reviews.llvm.org/D88555
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was removedmlir/include/mlir/Dialect/Affine/IR/AffineOpsBase.td
The file was modifiedmlir/include/mlir/Dialect/GPU/ParallelLoopMapperAttr.td
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
Commit dc261d23d07cccfa7b10a3d1a43903138aee94dc by ro
[sanitizers] Fix internal__exit on Solaris
`TestCases/log-path_test.cpp` currently `FAIL`s on Solaris:

  $ env ASAN_OPTIONS=log_path=`for((i=0;i<10000;i++)); do echo -n $i; done`  ./log-path_test.cpp.tmp
  ==5031==ERROR: Path is too long: 01234567...
  Segmentation Fault (core dumped)

The `SEGV` happens here:

  Thread 2 received signal SIGSEGV, Segmentation fault.
  [Switching to Thread 1 (LWP 1)]
  0x00000000 in ?? ()
  (gdb) where
  #0  0x00000000 in ?? ()
  #1  0x080a1e63 in __interceptor__exit (status=1)
      at /vol/gcc/src/llvm/llvm/local/projects/compiler-rt/lib/asan/../sanitizer_common/sanitizer_common_interceptors.inc:3808
  #2  0x08135ea8 in __sanitizer::internal__exit (exitcode=1)
      at /vol/gcc/src/llvm/llvm/local/projects/compiler-rt/lib/sanitizer_common/sanitizer_solaris.cc:139

when `__interceptor__exit` tries to call `__interception::real__exit` which
is `NULL` at this point because the interceptors haven't been initialized yet.

Ultimately, the problem lies elsewhere, however: `internal__exit` in
`sanitizer_solaris.cpp` calls `_exit` itself since there doesn't exit a
non-intercepted version in `libc`.  Using the `syscall` interface instead
isn't usually an option on Solaris because that interface isn't stable.
However, in the case of `SYS_exit` it can be used nonetheless: `SYS_exit`
has remained unchanged since at least Solaris 2.5.1 in 1996, and this is
what this patch does.

Tested on `amd64-pc-solaris2.11`.

Differential Revision: https://reviews.llvm.org/D88404
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_solaris.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
Commit 944691f0b7fa8d99790a4544545e55f014c37295 by Xiangling.Liao
[NFC][FE] Replace TypeSize with StorageUnitSize

On some targets like AIX, last bitfield size is not always equal to last
bitfield type size. Some bitfield like bool will have the same alignment
as [unsigned]. So we'd like to use a more general term `StorageUnit` to
replace type in this field.

Differential Revision: https://reviews.llvm.org/D88260
The file was modifiedclang/lib/AST/RecordLayoutBuilder.cpp
Commit 89baeaef2fa9a2441d087a218ac82e11a5d4e548 by Matthew.Arsenault
Reapply "RegAllocFast: Rewrite and improve"

This reverts commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4.
The file was modifiedllvm/test/CodeGen/AMDGPU/spill192.mir
The file was modifiedllvm/test/CodeGen/SystemZ/swift-return.ll
The file was modifiedllvm/test/DebugInfo/X86/pieces-1.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
The file was modifiedllvm/test/CodeGen/X86/pr32241.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-fastisel.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx-args.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
The file was modifiedllvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
The file was modifiedllvm/test/CodeGen/Mips/msa/ldr_str.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
The file was modifiedllvm/test/CodeGen/X86/atomic32.ll
The file was modifiedllvm/test/CodeGen/X86/pr30430.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
The file was modifiedllvm/test/CodeGen/X86/stack-protector-msvc.ll
The file was modifiedllvm/test/CodeGen/ARM/stack-guard-reassign.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
The file was modifiedllvm/test/CodeGen/X86/swifterror.ll
The file was modifiedllvm/test/DebugInfo/X86/spill-indirect-nrvo.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic.ll
The file was modifiedllvm/test/DebugInfo/X86/reference-argument.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
The file was modifiedllvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
The file was modifiedllvm/test/CodeGen/X86/phys-reg-local-regalloc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/addegluecrash.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll
The file was modifiedllvm/test/CodeGen/ARM/pr47454.ll
The file was modifiedllvm/test/DebugInfo/X86/subreg.ll
The file was modifiedllvm/test/CodeGen/SPARC/fp16-promote.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/CodeGen/ARM/ldrd.ll
The file was addedllvm/test/CodeGen/X86/bug47278-eflags-error.mir
The file was modifiedllvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
The file was modifiedllvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr.mir
The file was modifiedllvm/test/CodeGen/X86/swift-return.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll
The file was modifiedllvm/test/CodeGen/X86/pr32345.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-m0.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/builtin-return-address-pacret.ll
The file was modifiedllvm/test/CodeGen/AArch64/cmpxchg-O0.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic-min-max.ll
The file was modifiedllvm/test/CodeGen/X86/pr32340.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
The file was modifiedllvm/test/CodeGen/X86/atomic64.ll
The file was modifiedllvm/test/CodeGen/X86/pr32451.ll
The file was modifiedllvm/test/DebugInfo/X86/prologue-stack.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-overflow-toc.py
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/X86/pr11415.ll
The file was modifiedllvm/test/CodeGen/X86/pr27591.ll
The file was modifiedllvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll
The file was modifiedllvm/test/DebugInfo/X86/dbg-declare-arg.ll
The file was modifiedllvm/test/CodeGen/SystemZ/swifterror.ll
The file was modifiedllvm/test/CodeGen/Mips/implicit-sret.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp64-to-int16.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-loads.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vector-spill.ll
The file was modifiedllvm/test/CodeGen/ARM/legalize-bitcast.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
The file was modifiedllvm/test/CodeGen/Mips/copy-fp64.ll
The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
The file was modifiedllvm/test/CodeGen/PowerPC/anon_aggr.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
The file was modifiedllvm/test/CodeGen/AArch64/swift-return.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll
The file was modifiedllvm/test/CodeGen/Mips/micromips-eva.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
The file was modifiedllvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
The file was modifiedllvm/test/CodeGen/X86/crash-O0.ll
The file was modifiedllvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address_pic.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select.ll
The file was modifiedlldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
The file was modifiedllvm/test/CodeGen/ARM/Windows/alloca.ll
The file was modifiedllvm/test/CodeGen/PowerPC/elf-common.ll
The file was modifiedllvm/test/CodeGen/X86/pr44749.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic64.ll
The file was modifiedllvm/test/DebugInfo/ARM/prologue_end.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll
The file was modifiedllvm/test/DebugInfo/AArch64/prologue_end.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select-sse.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-x86-64.ll
The file was modifiedllvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
The file was modifiedllvm/test/CodeGen/PowerPC/popcount.ll
The file was modifiedllvm/test/DebugInfo/AArch64/frameindices.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
The file was modifiedllvm/test/CodeGen/X86/pr34592.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_constants.ll
The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes.ll
The file was modifiedllvm/test/CodeGen/X86/x86-64-intrcc.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved.ll
The file was modifiedllvm/test/CodeGen/ARM/crash-greedy-v6.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
The file was modifiedllvm/test/CodeGen/ARM/cmpxchg-O0.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
The file was modifiedllvm/test/CodeGen/X86/avx-load-store.ll
The file was addedllvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
The file was modifiedllvm/test/CodeGen/X86/atomic-monotonic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
The file was modifiedllvm/test/CodeGen/PowerPC/stack-guard-reassign.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll
The file was modifiedllvm/test/CodeGen/X86/volatile.ll
The file was modifiedllvm/test/DebugInfo/Mips/prologue_end.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
The file was modifiedllvm/test/DebugInfo/X86/parameters.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/AArch64/br-cond-not-merge.ll
The file was modifiedllvm/test/CodeGen/ARM/swifterror.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_split_because_of_memsize_or_align.ll
The file was modifiedllvm/test/CodeGen/Thumb2/high-reg-spill.mir
The file was modifiedllvm/test/CodeGen/X86/pr32284.ll
The file was modifiedllvm/test/CodeGen/X86/pr32484.ll
The file was modifiedllvm/test/CodeGen/ARM/debug-info-blocks.ll
The file was modifiedllvm/test/CodeGen/AArch64/swifterror.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll
The file was modifiedllvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
The file was modifiedllvm/test/CodeGen/X86/pr1489.ll
The file was modifiedllvm/test/CodeGen/X86/pr42452.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll
The file was addedllvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
The file was modifiedllvm/test/CodeGen/X86/x86-32-intrcc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx.ll
The file was addedllvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-null.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
The file was modifiedllvm/test/DebugInfo/X86/sret.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
The file was modifiedllvm/test/DebugInfo/Mips/delay-slot.ll
The file was modifiedllvm/test/CodeGen/X86/pr47000.ll
The file was modifiedllvm/test/CodeGen/X86/atomic6432.ll
The file was modifiedllvm/test/CodeGen/X86/win64_eh.ll
The file was modifiedllvm/test/CodeGen/ARM/thumb-big-stack.ll
The file was addedllvm/test/CodeGen/PowerPC/spill-nor0.mir
The file was modifiedllvm/test/CodeGen/X86/pr30813.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-vararg.ll
The file was modifiedllvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll
The file was modifiedllvm/test/CodeGen/PowerPC/spill-nor0.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/var_arg.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-nontemporal.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctpop.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
The file was modifiedllvm/test/CodeGen/X86/pr34653.ll
The file was modifiedllvm/test/DebugInfo/X86/fission-ranges.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
The file was modifiedllvm/test/CodeGen/Mips/atomicCmpSwapPW.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
The file was modifiedllvm/test/CodeGen/X86/pr39733.ll
The file was addedllvm/test/CodeGen/X86/bug47278.mir
Commit a66fca44ac926b25820f0e9344db1947d966291b by Matthew.Arsenault
RegAllocFast: Add extra DBG_VALUE for live out spills

This allows LiveDebugValues to insert the proper DBG_VALUEs in live
out blocks if a spill is inserted before the use of a
register. Previously, this would see the register use as the last
DBG_VALUE, even though the stack slot should be treated as the live
out value.

This avoids an lldb test regression when D52010 is re-applied.
The file was modifiedllvm/test/DebugInfo/X86/sret.ll
The file was addedllvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
The file was modifiedllvm/test/DebugInfo/X86/fission-ranges.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/DebugInfo/X86/parameters.ll
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
The file was modifiedllvm/test/DebugInfo/X86/subreg.ll
Commit d93459992e559e774e7b14208e5bd8bf27a58280 by Matthew.Arsenault
LiveDebugValues: Fix typos and indentation
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
Commit 5aa1119537fe6569b54d0da4d9d649a6940decff by Matthew.Arsenault
GlobalISel: Assert if MoreElements uses a non-vector type
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
Commit 2ef73025afda6481625b74eb99cdbc2eb1cfef95 by llvm-dev
[InstCombine] Remove %tmp variable names from bswap-fold tests

Appease update_test_checks script that was complaining about potential %TMP clashes
The file was modifiedllvm/test/Transforms/InstCombine/bswap-fold.ll
Commit 3a7487f903e2a6be29de39058eee2372e30798d5 by Xiangling.Liao
[FE] Use preferred alignment instead of ABI alignment for complete object when applicable

On some targets, preferred alignment is larger than ABI alignment in some cases. For example,
on AIX we have special power alignment rules which would cause that. Previously, to support
those cases, we added a “PreferredAlignment” field in the `RecordLayout` to store the AIX
special alignment values in “PreferredAlignment” as the community suggested.

However, that patch alone is not enough. There are places in the Clang where `PreferredAlignment`
should have been used instead of ABI-specified alignment. This patch is aimed at fixing those
spots.

Differential Revision: https://reviews.llvm.org/D86790
The file was modifiedclang/lib/CodeGen/ItaniumCXXABI.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/lib/CodeGen/CGExprCXX.cpp
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was addedclang/test/CodeGen/aix-alignment.c
The file was addedclang/test/CodeGenCXX/aix-alignment.cpp
The file was modifiedclang/lib/AST/ASTContext.cpp
Commit 892fdc923f06adbef507ebe594fa7b48224d93f0 by ravishankarm
[mlir][Linalg] Generalize the logic to compute reassociation maps
while folding tensor_reshape op.

While folding reshapes that introduce unit extent dims, the logic to
compute the reassociation maps can be generalized to handle some
corner cases, for example, when the folded shape still has unit-extent
dims but corresponds to folded unit extent dims of the expanded shape.

Differential Revision: https://reviews.llvm.org/D88521
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
Commit b85de2c69cf3d6fbc2ad3439a6224667a58f704c by llvm-dev
[InstCombine] Add bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector tests

Add tests showing failure to correctly fold vector bswap(trunc(bswap(x))) intrinsic patterns
The file was modifiedllvm/test/Transforms/InstCombine/bswap-fold.ll
Commit 323d08e50a7bb80786dc00a8ade6ae49e1358393 by llvm-dev
[InstCombine] Fix bswap(trunc(bswap(x))) -> trunc(lshr(x, c)) vector support

Use getScalarSizeInBits not getPrimitiveSizeInBits to determine the shift value at the element level.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/bswap-fold.ll
Commit 2c394bd4071d32000e2eed0f7d90fe7c576d7050 by benny.kra
[PowerPC] Avoid unused variable warning in Release builds

PPCFrameLowering.cpp:632:8: warning: unused variable 'isAIXABI' [-Wunused-variable]
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Commit 052c5bf40a9fc9ffe1bb2669763d8a0d2dea2b2e by zarko
[PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9

It looks like in some circumstances when compiling with `-mcpu=pwr9` we create an EXTSWSLI node when which causes llc to fail. No such error occurs in pwr8 or lower.

This occurs in 32BIT AIX and BE Linux. the cause seems to be that the default return in combineSHL is to create an EXTSWSLI node.  Adding a check for whether we are in PPC64 before that fixes the issue.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D87046
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll
Commit f425418fc4ebd989c6c3d59d20e7fe37cb29259c by llvm-dev
[InstCombine] Add tests for 'partial' bswap patterns

As mentioned on PR47191, if we're bswap'ing some bytes and the zero'ing the remainder we can perform this as a bswap+mask which helps us match 'partial' bswaps as a first step towards folding into a more complex bswap pattern.
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit d6de40f8865e2c016731f9b63d8a0a218ce1b74f by mtrofin
[NFC][regalloc] Make VirtRegAuxInfo part of allocator state

All the state of VRAI is allocator-wide, so we can avoid creating it
every time we need it. In addition, the normalization function is
allocator-specific. In a next change, we can simplify that design in
favor of just having it as a virtual member.

Differential Revision: https://reviews.llvm.org/D88499
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was modifiedllvm/lib/CodeGen/CalcSpillWeights.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocBasic.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocPBQP.cpp
The file was modifiedllvm/include/llvm/CodeGen/CalcSpillWeights.h
Commit 05ae04c396519cca9ef50d3b9cafb0cd9c87d1d7 by simon.moll
[DA][SDA] SyncDependenceAnalysis re-write

This patch achieves two things:
1. It breaks up the `join_blocks` interface between the SDA to the DA to
   return two separate sets for divergent loops exits and divergent,
disjoint path joins.
2. It updates the SDA algorithm to run in O(n) time and improves the
   precision on divergent loop exits.

This fixes `https://bugs.llvm.org/show_bug.cgi?id=46372` (by virtue of
the improved `join_blocks` interface) and revealed an imprecise expected
result in the `Analysis/DivergenceAnalysis/AMDGPU/hidden_loopdiverge.ll`
test.

Reviewed By: sameerds

Differential Revision: https://reviews.llvm.org/D84413
The file was modifiedllvm/lib/Analysis/DivergenceAnalysis.cpp
The file was modifiedllvm/test/Analysis/DivergenceAnalysis/AMDGPU/hidden_loopdiverge.ll
The file was modifiedllvm/include/llvm/Analysis/SyncDependenceAnalysis.h
The file was modifiedllvm/lib/Analysis/SyncDependenceAnalysis.cpp
The file was modifiedllvm/test/Analysis/DivergenceAnalysis/AMDGPU/trivial-join-at-loop-exit.ll
The file was modifiedllvm/include/llvm/Analysis/DivergenceAnalysis.h
Commit 1034262e0a38f0bd755e68aa41b6bb856ebd2eb8 by jam
[VE] Support TargetBlockAddress

Change to handle TargetBlockAddress and add a regression test for it.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D88576
The file was addedllvm/test/CodeGen/VE/blockaddress.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was modifiedllvm/lib/Target/VE/VEMCInstLower.cpp
Commit 4fbd83c716dbc1d68e0aac5d71d201b664762489 by aeubanks
[ObjCARCAA][NewPM] Add already ported objc-arc-aa to PassRegistry.def

Also add missing AnalysisKey definition.
The file was modifiedllvm/lib/Analysis/ObjCARCAliasAnalysis.cpp
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/test/Transforms/ObjCARC/gvn.ll
The file was modifiedllvm/lib/Passes/PassRegistry.def
Commit dd4fb7c8cfe394a3290bd19a1eac03435472ccfa by clementval
[mlir][openacc] Remove -allow-unregistred-dialect from ops and invalid tests

Switch to a dummy op in the test dialect so we can remove the -allow-unregistred-dialect
on ops.mlir and invalid.mlir. Change after comment on D88272.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D88587
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir
The file was modifiedmlir/test/Dialect/OpenACC/invalid.mlir
Commit 4fcd1a8e6528ca42fe656f2745e15d2b7f5de495 by vyng
[llvm-exegesis] Add option to check the hardware support for a given feature before benchmarking.

This is mostly for the benefit of the LBR latency mode.
Right now, it performs no checking. If this is run on non-supported hardware, it will produce all zeroes for latency.

Differential Revision: https://reviews.llvm.org/D85254
The file was modifiedllvm/tools/llvm-exegesis/lib/Target.h
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/Target.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/X86Counter.h
The file was modifiedllvm/tools/llvm-exegesis/llvm-exegesis.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/X86Counter.cpp
The file was modifiedllvm/test/tools/llvm-exegesis/X86/lbr/lit.local.cfg