SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [NFCI][clang-tidy] FunctionCognitiveComplexityCheck::check(): try to fix windows arm build bots (details)
  2. [InstCombine] recognizeBSwapOrBitReverseIdiom - support for 'partial' bswap patterns (PR47191) (Reapplied) (details)
  3. modernize-use-trailing-return-type fix for PR44206 (details)
  4. [flang][NFC] Fix build errors for clang-10 (details)
  5. [InstCombine] recognizeBSwapOrBitReverseIdiom - use generic CreateIntegerCast (details)
  6. Add a break statement to appease the build bots; NFC (details)
  7. [InstCombine] recognizeBSwapOrBitReverseIdiom - add vector support (details)
  8. [ARM] Fix pointer offset when splitting stores from VMOVDRR (details)
  9. Add indented raw_ostream class (details)
  10. [InstCombine] Add or(shl(v,and(x,bw-1)),lshr(v,bw-and(x,bw-1))) rotate tests (details)
  11. Revert "Add indented raw_ostream class" (details)
  12. [Analysis] resolveAllCalls - fix use after std::move warning. NFCI. (details)
  13. [InstCombine] Add tests for or(shl(x,c1),lshr(y,c2)) patterns that could fold to funnel shifts (details)
  14. [asan] Stop instrumenting user-defined ELF sections (details)
  15. [lldb] [Process/NetBSD] Fix reading FIP/FDP registers (details)
  16. [lldb] [Process/NetBSD] Fix crash on unsupported i386 regs (details)
  17. [lldb] [test/Register] Add read/write tests for x87 regs (details)
  18. [clang][NFC] Change a mention of `objc_static_protocol` to `non_runtime` (details)
  19. Revert "[Driver] Move detectLibcxxIncludePath to ToolChain" (details)
  20. [AArch64] Match the windows canonical callee saved register order (details)
  21. [AArch64] Allow pairing lr with other GPRs for WinCFI (details)
  22. [AArch64] Prefer prologues with sp adjustments merged into stp/ldp for WinCFI, if optimizing for size (details)
  23. [LV] Add another test case with unsinkable first-order recurrences. (details)
  24. [NFC][PhaseOrdering] Add a test showing new inttoptr casts after SROA due to InstCombine (PR47592) (details)
  25. [NFC][InstCombine] Autogenerate a few tests being affected by an upcoming patch (details)
  26. [VPlan] Properly update users when updating operands. (details)
  27. [lldb] [test/Register] Mark new FP reg tests XFAIL on Windows (details)
  28. [MC] Assert that MCRegUnitIterator operates over MCRegisters (details)
  29. [Object][MachO] Refactor MachOUniversalWriter (details)
  30. Add indented raw_ostream class (details)
  31. [X86] Add X86ISD opcodes for the Key Locker AESENC*KL and AESDEC*KL instructions (details)
Commit 1596cc83509342eb37dbfe6b95e906759afc6741 by lebedev.ri
[NFCI][clang-tidy] FunctionCognitiveComplexityCheck::check(): try to fix windows arm build bots

http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/1482/steps/build-llvm-project/logs/stdio
http://lab.llvm.org:8011/builders/llvm-clang-win-x-aarch64/builds/3285/steps/build-llvm-project/logs/stdio
The file was modifiedclang-tools-extra/clang-tidy/readability/FunctionCognitiveComplexityCheck.cpp
Commit 3aa93f690b097257e9a2e48b133c4f413bc3ed92 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - support for 'partial' bswap patterns (PR47191) (Reapplied)

If we're bswap'ing some bytes and zero'ing the remainder we can perform this as a bswap+mask which helps us match 'partial' bswaps as a first step towards folding into a more complex bswap pattern.

Reapplied with early-out if recognizeBSwapOrBitReverseIdiom collects a source wider than the result type.

Differential Revision: https://reviews.llvm.org/D88578
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 07028cd5dbb8417fb41121a7e75290fab00f65fc by aaron
modernize-use-trailing-return-type fix for PR44206

Prevent rewrite when an unqualified id in a typedef type collides
with a function argument name. Fixes PR44206.
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/modernize-use-trailing-return-type.cpp
The file was modifiedclang-tools-extra/clang-tidy/modernize/UseTrailingReturnTypeCheck.cpp
Commit 35a2a042ddd127205455fc26ae516ccc513fd5cf by andrzej.warzynski
[flang][NFC] Fix build errors for clang-10

This patch fixes one worning. Since Flang sets `-Werror`, that's
sufficient for a build to fail. As per flang/README.md, Clang-10 is one
of the officially supported compilers.

Differential Revision: https://reviews.llvm.org/D88723
The file was modifiedflang/lib/Lower/OpenACC.cpp
Commit 347fd9955af3fff2622d8349a59974ecc2237ec1 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - use generic CreateIntegerCast

Try to appease buildbots breakages due to D88578
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 089e628b61f929ccd26565cd4118395f0a0273c3 by aaron
Add a break statement to appease the build bots; NFC
The file was modifiedclang-tools-extra/clang-tidy/modernize/UseTrailingReturnTypeCheck.cpp
Commit aacfe2be53d441d256091b2b495875a69fc2f285 by llvm-dev
[InstCombine] recognizeBSwapOrBitReverseIdiom - add vector support

Add basic vector handling to recognizeBSwapOrBitReverseIdiom/collectBitParts - this works at the element level, all vector element operations must match (splat constants etc.) and there is no cross-element support (insert/extract/shuffle etc.).
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit 7feafa0286f1f5e059d70a9a9f4168f32db3b444 by david.green
[ARM] Fix pointer offset when splitting stores from VMOVDRR

We were not accounting for the pointer offset when splitting a store from
a VMOVDRR node, which could lead to incorrect aliasing info. In this
case it is the fneg via integer arithmetic that gives us a store->load
pair that we started getting wrong.

Differential Revision: https://reviews.llvm.org/D88653
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/vmovdrroffset.ll
Commit 78530ce65375fa02bc96019e5cc9d73db8adaca4 by jpienaar
Add indented raw_ostream class

Class simplifies keeping track of the indentation while emitting. For every new line the current indentation is simply prefixed (if not at start of line, then it just emits as normal). Add a simple Region helper that makes it easy to have the C++ scope match the emitted scope.

Use this in op doc generator and rewrite generator.

Differential Revision: https://reviews.llvm.org/D84107
The file was modifiedmlir/tools/mlir-tblgen/CMakeLists.txt
The file was modifiedmlir/lib/Support/CMakeLists.txt
The file was modifiedmlir/tools/mlir-tblgen/OpDocGen.cpp
The file was addedmlir/unittests/Support/CMakeLists.txt
The file was modifiedmlir/tools/mlir-tblgen/RewriterGen.cpp
The file was addedmlir/lib/Support/IndentedOstream.cpp
The file was addedmlir/include/mlir/Support/IndentedOstream.h
The file was addedmlir/unittests/Support/IndentedOstreamTest.cpp
Commit b82a7486d108a708f00c00feed784f34711300db by llvm-dev
[InstCombine] Add or(shl(v,and(x,bw-1)),lshr(v,bw-and(x,bw-1))) rotate tests

If we know the shift amount is less than the bitwidth we should be able to convert this to a rotate/funnel shift
The file was modifiedllvm/test/Transforms/InstCombine/rotate.ll
Commit be185b6a7355fdfeb1c31df2e1272366fe58b01f by jpienaar
Revert "Add indented raw_ostream class"

This reverts commit 78530ce65375fa02bc96019e5cc9d73db8adaca4.

Fails on shared_lib build.
The file was removedmlir/include/mlir/Support/IndentedOstream.h
The file was modifiedmlir/lib/Support/CMakeLists.txt
The file was modifiedmlir/tools/mlir-tblgen/RewriterGen.cpp
The file was removedmlir/unittests/Support/IndentedOstreamTest.cpp
The file was removedmlir/unittests/Support/CMakeLists.txt
The file was modifiedmlir/tools/mlir-tblgen/OpDocGen.cpp
The file was modifiedmlir/tools/mlir-tblgen/CMakeLists.txt
The file was removedmlir/lib/Support/IndentedOstream.cpp
Commit dca4b7130de547860925631295acfce33130a100 by llvm-dev
[Analysis] resolveAllCalls - fix use after std::move warning. NFCI.

We can't use Use.Calls after its std::move()'d to TmpCalls as it will be in an undefined state. Instead, swap with the known empty map in TmpCalls so we can then safely emplace_back into the now empty Use.Calls.

Fixes clang static analyzer warning.
The file was modifiedllvm/lib/Analysis/StackSafetyAnalysis.cpp
Commit 53fc426088d7e48272bfc37a3881a7a6fe405940 by llvm-dev
[InstCombine] Add tests for or(shl(x,c1),lshr(y,c2)) patterns that could fold to funnel shifts

Some initial test coverage toward fixing PR46896 - these are just copied from rotate.ll
The file was addedllvm/test/Transforms/InstCombine/funnel.ll
Commit 66e493f81e8e27b4a498a6dac54d404c2333fa5e by mgorny
[asan] Stop instrumenting user-defined ELF sections

Do not instrument user-defined ELF sections (whose names resemble valid
C identifiers).  They may have special use semantics and modifying them
may break programs.  This is e.g. the case with NetBSD __link_set API
that expects these sections to store consecutive array elements.

Differential Revision: https://reviews.llvm.org/D76665
The file was modifiedllvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
The file was addedllvm/test/Instrumentation/AddressSanitizer/instrument-section-invalid-c-ident.ll
The file was addedllvm/test/Instrumentation/AddressSanitizer/do-not-instrument-netbsd-link_set.ll
Commit 80b108f404fc9e88889df7247f6ae9697083cbda by mgorny
[lldb] [Process/NetBSD] Fix reading FIP/FDP registers

Fix reading FIP/FDP registers to correctly return segment and offset
parts.  On amd64, this roughly matches the Linux behavior of splitting
the 64-bit FIP/FDP into two halves, and putting the higher 32 bits
into f*seg and lower into f*off.  Well, actually we use only 16 bits
of higher half but the CPUs do not seem to handle more than that anyway.

Differential Revision: https://reviews.llvm.org/D88681
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
Commit 9821632056dce9e2150bab9c0fbd9b2c7da64258 by mgorny
[lldb] [Process/NetBSD] Fix crash on unsupported i386 regs

Multiple fixes related to bugs discovered while debugging a crash
when reading all registers on i386.

The underlying problem was that GetSetForNativeRegNum() did not account
for MPX registers on i386, and since it only compared against upper
bounds of each known register set, the MPX registers were classified
into the wrong set and therefore considered supported.  However, they
were not expected in RegNumX86ToX86_64() and caused the assertion
to fail.

This includes:

- adding (unused) i386 → x86_64 translations for MPX registers
- fixing GetSetForNativeRegNum() to check both lower and upper bound
  for register sets, to avoid wrongly classifying unhandled register
  sets
- adding missing range check for MPX registers on i386
- renaming k_last_mpxr to k_last_mpxr_i386 for consistency
- replacing return-assertions with llvm_unreachable() and adding more
  checks for unexpected parameters

Differential Revision: https://reviews.llvm.org/D88682
The file was modifiedlldb/source/Plugins/Process/Utility/lldb-x86-register-enums.h
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
Commit 381bdc75ee2ca2fb9784ffb2f6b90accd8eab3b6 by mgorny
[lldb] [test/Register] Add read/write tests for x87 regs

Add a partial read/write tests for x87 FPU registers.  This includes
reading and writing ST registers, control registers and floating-point
exception data registers (fop, fip, fdp).

The tests assume the current (roughly incorrect) behavior of reporting
the 'abridged' 8-bit ftag state as 16-bit ftag.  They also assume Linux
plugin behavior of reporting fip/fdp split into halves as (fiseg, fioff)
and (foseg, fooff).

Differential Revision: https://reviews.llvm.org/D88583
The file was addedlldb/test/Shell/Register/Inputs/x86-fp-write.cpp
The file was addedlldb/test/Shell/Register/x86-fp-write.test
The file was addedlldb/test/Shell/Register/x86-64-fp-write.test
The file was addedlldb/test/Shell/Register/x86-fp-read.test
The file was addedlldb/test/Shell/Register/Inputs/x86-fp-read.cpp
Commit fcb0ab59335be185e05258c905ef57da9e7f3324 by nathan
[clang][NFC] Change a mention of `objc_static_protocol` to `non_runtime`
The file was modifiedclang/include/clang/AST/DeclObjC.h
Commit ba60dc0aa75e86165e260b2c08afafd1c394e95a by thakis
Revert "[Driver] Move detectLibcxxIncludePath to ToolChain"

This reverts commit e25bf2592060e7751f8b14522c97081ce2047175.
Breaks tests on Windows, see comments on https://reviews.llvm.org/D88452
The file was modifiedclang/lib/Driver/ToolChains/Fuchsia.cpp
The file was modifiedclang/lib/Driver/ToolChains/Gnu.cpp
The file was modifiedclang/lib/Driver/ToolChain.cpp
The file was removedclang/test/Driver/Inputs/basic_fuchsia_tree/include/c++/v1/.keep
The file was modifiedclang/include/clang/Driver/ToolChain.h
Commit 3780a4e568ac763567cc6987372e04f9e3c68ff9 by martin
[AArch64] Match the windows canonical callee saved register order

On windows, the callee saved registers in a canonical prologue are
ordered starting from a lower register number at a lower stack
address (with the possible gap for aligning the stack at the top);
this is the opposite order that llvm normally produces.

To achieve this, reverse the order of the registers in the
assignCalleeSavedSpillSlots callback, to get the stack objects
laid out by PrologEpilogInserter in the right order, and adjust
computeCalleeSaveRegisterPairs to lay them out from the bottom up.

This allows generated prologs more often to match the format that
allows the unwind info to be written as packed info.

Differential Revision: https://reviews.llvm.org/D88677
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame1.mir
The file was addedllvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame2.mir
The file was modifiedllvm/test/CodeGen/AArch64/sponentry.ll
The file was modifiedllvm/test/CodeGen/AArch64/win64_vararg.ll
The file was modifiedllvm/test/CodeGen/AArch64/seh-finally.ll
The file was modifiedllvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame0.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame5.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame3.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame4.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh-try-catch-realign.ll
The file was modifiedllvm/test/CodeGen/AArch64/wineh-try-catch.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
Commit 890af2f003c83349ff5917d80023b8b796f76489 by martin
[AArch64] Allow pairing lr with other GPRs for WinCFI

This saves one instruction per prologue/epilogue for any function with
an odd number of callee-saved GPRs, but more importantly, allows such
functions to match the packed unwind format.

Differential Revision: https://reviews.llvm.org/D88699
The file was addedllvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir
The file was addedllvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir
The file was addedllvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/win64_vararg.ll
Commit 7d07405761aec8434a0cdb1c5644823a394f7def by martin
[AArch64] Prefer prologues with sp adjustments merged into stp/ldp for WinCFI, if optimizing for size

This makes the prologue match the windows canonical layout, for
cases without a frame pointer.

This can potentially be a slower (a longer dependency chain of the
sp register, and potentially one arithmetic operation more on some
cores), but gives notable size improvements.

The previous two commits shrinks a 166 KB xdata section by 49 KB,
and if the change from this commit is enabled, it shrinks the xdata
section by another 25 KB.

In total, since the start of the recent arm64 unwind info cleanups
and optimizations (since before commit 37ef743cbf3), the xdata+pdata
sections of the same test DLL has shrunk from 407 KB in total
originally, to 163 KB now.

Differential Revision: https://reviews.llvm.org/D88701
The file was addedllvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
Commit ef72591de971ee22dd47a949583fd1be38ba0d1b by flo
[LV] Add another test case with unsinkable first-order recurrences.
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
Commit 1038ce4b6bf11c9615e60b503bdb253a000a6d90 by lebedev.ri
[NFC][PhaseOrdering] Add a test showing new inttoptr casts after SROA due to InstCombine (PR47592)

We could either try to make SROA more picky to the new type
and/or prevent InstCombine from creating the original problem (converting load-stores to operate on ints),
and/or make InstCombine recover the situation by cleaning up all that cruft.
The file was addedllvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
Commit cd20c26622287f29f96bf8012d5aa0bd9774c7bc by lebedev.ri
[NFC][InstCombine] Autogenerate a few tests being affected by an upcoming patch
The file was modifiedllvm/test/Transforms/InstCombine/loadstore-metadata.ll
The file was modifiedllvm/test/Transforms/InstCombine/atomic.ll
The file was modifiedllvm/test/Transforms/InstCombine/non-integral-pointers.ll
Commit 82dcd383c422f03c2b399af5b94701365cdf1afa by flo
[VPlan] Properly update users when updating operands.

When updating operands of a VPUser, we also have to adjust the list of
users for the new and old VPValues. This is required once we start
transitioning recipes to become VPValues.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Commit 508ac0ec13c1c56029fd2390a2e14c1b2ea84b73 by mgorny
[lldb] [test/Register] Mark new FP reg tests XFAIL on Windows
The file was modifiedlldb/test/Shell/Register/x86-64-fp-write.test
The file was modifiedlldb/test/Shell/Register/x86-fp-write.test
The file was modifiedlldb/test/Shell/Register/x86-fp-read.test
Commit 0a3523299dec61f2e6eb2a28fdecd25360e8b6d8 by mtrofin
[MC] Assert that MCRegUnitIterator operates over MCRegisters

The signature of the ctor expects a MCRegister, but currently any
unsigned value can be converted to a MCRegister.

This patch checks that indeed the provided value is a physical register
only. We want to eventually stop implicitly converting unsigned or
Register to MCRegister (which is incorrect). The next step after this
patch is changing uses of MCRegUnitIterator to explicitly cast Register
or unsigned values to MCRegister. To that end, this patch also
introduces 2 APIs that make that conversion checked and explicit.

Differential Revision: https://reviews.llvm.org/D88705
The file was modifiedllvm/include/llvm/CodeGen/Register.h
The file was modifiedllvm/include/llvm/MC/MCRegister.h
The file was modifiedllvm/include/llvm/MC/MCRegisterInfo.h
Commit d20c602aad7cc7d116df3bf8c17c533ef361ee61 by alexshap
[Object][MachO] Refactor MachOUniversalWriter

This diff refactors writeUniversalBinary and adds writeUniversalBinaryToBuffer.
This is a preparation for adding support for universal binaries to llvm-objcopy.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D88372
The file was modifiedllvm/lib/Object/MachOUniversalWriter.cpp
The file was modifiedllvm/include/llvm/Object/MachOUniversalWriter.h
Commit 9b851527d53345c4a5d56a909dfa1ca7f59a0c11 by jpienaar
Add indented raw_ostream class

Class simplifies keeping track of the indentation while emitting. For every new line the current indentation is simply prefixed (if not at start of line, then it just emits as normal). Add a simple Region helper that makes it easy to have the C++ scope match the emitted scope.

Use this in op doc generator and rewrite generator.

This reverts revert commit be185b6a7355fdfeb1c31df2e1272366fe58b01f addresses shared lib failure by fixing up cmake files.

Differential Revision: https://reviews.llvm.org/D84107
The file was modifiedmlir/lib/Support/CMakeLists.txt
The file was modifiedmlir/tools/mlir-tblgen/RewriterGen.cpp
The file was addedmlir/unittests/Support/IndentedOstreamTest.cpp
The file was addedmlir/unittests/Support/CMakeLists.txt
The file was modifiedmlir/tools/mlir-tblgen/OpDocGen.cpp
The file was addedmlir/include/mlir/Support/IndentedOstream.h
The file was modifiedmlir/tools/mlir-tblgen/CMakeLists.txt
The file was addedmlir/lib/Support/IndentedOstream.cpp
Commit adccc0bfa301005367d6b89a3aacc07ef0166e64 by craig.topper
[X86] Add X86ISD opcodes for the Key Locker AESENC*KL and AESDEC*KL instructions

Instead of emitting MachineSDNodes during lowering, emit X86ISD
opcodes. These opcodes will either be selected by tablegen
patterns or custom selection code.

Emitting MachineSDNodes during lowering is uncommon so this makes
things more consistent. It also allows selectAddr to be called to
perform address matching during instruction selection.

I had trouble getting tablegen to accept XMM0-XMM7 as results in
an isel pattern for the WIDE instructions so I had to use custom
instruction selection.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/test/CodeGen/X86/keylocker-intrinsics.ll
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was modifiedllvm/lib/Target/X86/X86InstrKL.td