Changes

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

[mlir][CAPI] Attribute set/remove on operations. (details)
[NFC] Add contributors names to CREDITS.TXT (details)
[llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. (details)
[clangd] Disambiguate overloads of std::move for header insertion. (details)
Rename the VECREDUCE_STRICT_{FADD,FMUL} SDNodes to VECREDUCE_SEQ_{FADD,FMUL}. (details)
[AMDGPU] Use default zero flag operands in flat scratch (details)
[LAA] Use DL to get element size for bound computation. (details)
[test][MC] Use %python in llvm/test/MC/COFF/bigobj.py (details)
[AMDGPU] Add tied operand to d16 scratch loads (details)
[mlir] Fix build after 322d0afd875df66b36e4810a2b95c20a8f22ab9b due to change in intrinsic overloads. (details)

Commit 4aa217160e5f06a96c6effc4950c3b402374de58 by stellaraccident [mlir][CAPI] Attribute set/remove on operations. * New functions: mlirOperationSetAttributeByName, mlirOperationRemoveAttributeByName * Also adds some IsNull checks and standardizes the rest to use "static inline" form, which makes them all non-opaque and not part of the ABI (which is desirable). Changes needed to resolve TODOs in npcomp PyTorch capture. Differential Revision: https://reviews.llvm.org/D88946
	mlir/test/CAPI/ir.c
	mlir/include/mlir-c/IR.h
	mlir/lib/CAPI/IR/IR.cpp
Commit 19bc894da12a9229b3e8cfb11a0281786f07ab6c by fanbo.meng [NFC] Add contributors names to CREDITS.TXT
	llvm/CREDITS.TXT
Commit 322d0afd875df66b36e4810a2b95c20a8f22ab9b by Amara Emerson [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. This change renames the intrinsics to not have "experimental" in the name. The autoupgrader will handle legacy intrinsics. Relevant ML thread: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140729.html Differential Revision: https://reviews.llvm.org/D88787
	llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
	llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
	llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
	llvm/test/Bitcode/upgrade-vecreduce-intrinsics.ll
	llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
	llvm/test/CodeGen/AArch64/arm64-vabs.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
	llvm/test/CodeGen/X86/vector-reduce-and.ll
	llvm/lib/Target/ARM/MVETailPredication.cpp
	llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-bit.ll
	llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
	mlir/include/mlir/Dialect/Vector/VectorOps.td
	llvm/docs/ReleaseNotes.rst
	llvm/test/CodeGen/AArch64/vecreduce-bool.ll
	llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
	llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
	llvm/test/Analysis/CostModel/X86/reduce-smax.ll
	llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
	llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
	llvm/test/Analysis/CostModel/X86/reduce-and.ll
	mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
	llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
	llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
	llvm/test/CodeGen/X86/vector-reduce-fmax.ll
	llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-reduce.ll
	llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
	llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
	llvm/test/Analysis/CostModel/X86/reduce-fmax.ll
	llvm/test/CodeGen/X86/haddsub.ll
	llvm/test/Transforms/SLPVectorizer/X86/reassociated-loads.ll
	llvm/lib/IR/AutoUpgrade.cpp
	llvm/test/CodeGen/AArch64/neon-dot-product.ll
	llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
	llvm/test/CodeGen/X86/vector-reduce-fmax-fmin-fast.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
	llvm/test/CodeGen/X86/vector-reduce-or.ll
	llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
	llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
	llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
	llvm/test/Analysis/CostModel/X86/reduce-or.ll
	llvm/test/Assembler/invalid-vecreduce.ll
	llvm/test/CodeGen/X86/vector-reduce-xor.ll
	llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
	llvm/test/Analysis/CostModel/ARM/reduce-smin.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
	llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
	llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-mul.ll
	llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll
	mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/tp-multiple-vpst.ll
	llvm/test/CodeGen/X86/vector-reduce-mul.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
	llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
	llvm/test/Analysis/CostModel/ARM/reduce-smax.ll
	llvm/test/Analysis/CostModel/AArch64/vector-reduce.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
	llvm/test/Analysis/CostModel/X86/reduce-smin.ll
	mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
	llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
	mlir/test/Conversion/VectorToLLVM/vector-reduction-to-llvm.mlir
	llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
	llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
	llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
	llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
	llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
	llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
	llvm/test/Transforms/LoopVectorize/X86/pr42674.ll
	llvm/test/CodeGen/X86/vector-reduce-fmul.ll
	llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
	llvm/test/CodeGen/X86/vector-reduce-smin.ll
	llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
	llvm/test/Analysis/CostModel/ARM/reduce-umin.ll
	llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll
	llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
	llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
	mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
	llvm/test/Analysis/CostModel/ARM/reduce-umax.ll
	llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
	llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
	llvm/test/Instrumentation/MemorySanitizer/experimental-reduce.ll
	llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
	llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
	llvm/test/Analysis/CostModel/X86/reduce-umax.ll
	llvm/test/Bitcode/upgrade-vecreduce-intrinsics.ll.bc
	llvm/test/CodeGen/X86/pr45378.ll
	mlir/integration_test/Dialect/LLVMIR/CPU/test-vector-reductions-fp.mlir
	llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll
	llvm/test/Analysis/CostModel/X86/reduce-fmin.ll
	llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
	llvm/test/CodeGen/X86/vector-reduce-and-cmp.ll
	llvm/include/llvm/IR/Intrinsics.td
	llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
	llvm/test/CodeGen/X86/vector-reduce-fadd.ll
	llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
	llvm/test/Transforms/SLPVectorizer/AArch64/gather-root.ll
	llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
	mlir/test/Target/llvmir-intrinsics.mlir
	llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
	llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll
	llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
	llvm/lib/Target/ARM/ARMTargetTransformInfo.h
	llvm/test/Instrumentation/MemorySanitizer/reduce.ll
	llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
	llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
	llvm/test/Analysis/CostModel/X86/reduce-umin.ll
	llvm/test/Transforms/SLPVectorizer/X86/reduction_loads.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
	llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
	llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
	llvm/test/Analysis/CostModel/ARM/reduce-add.ll
	llvm/test/CodeGen/X86/vector-reduce-fmin.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
	llvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll
	llvm/test/Transforms/InstCombine/vector-reductions.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
	llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
	llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
	llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
	llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
	llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
	llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
	llvm/test/CodeGen/Thumb2/mve-vaddv.ll
	llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
	llvm/test/Transforms/LoopVectorize/AArch64/reduction-small-size.ll
	llvm/test/CodeGen/Thumb2/mve-vmaxv.ll
	llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
	llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll
	mlir/integration_test/Dialect/LLVMIR/CPU/test-vector-reductions-int.mlir
	llvm/test/CodeGen/X86/vector-reduce-add.ll
	llvm/lib/IR/IRBuilder.cpp
	llvm/test/Analysis/CostModel/X86/reduce-xor.ll
	llvm/test/CodeGen/X86/vector-reduce-umax.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
	llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
	llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-reduce-mve-tail.ll
	llvm/lib/CodeGen/ExpandReductions.cpp
	llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
	llvm/test/CodeGen/AArch64/aarch64-addv.ll
	llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll
	llvm/test/Transforms/InstSimplify/ConstProp/vecreduce.ll
	llvm/lib/Analysis/ConstantFolding.cpp
	llvm/test/CodeGen/X86/vector-reduce-umin.ll
	llvm/test/Analysis/CostModel/X86/reduce-mul.ll
	llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
	llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
	llvm/test/CodeGen/X86/vector-reduce-smax.ll
	llvm/docs/LangRef.rst
	llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
	llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
	llvm/test/Analysis/CostModel/X86/reduce-add.ll
	llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
	llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
	llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
	llvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll
	llvm/include/llvm/CodeGen/BasicTTIImpl.h
	llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll
	llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
Commit 69daa368cad34c3cff7e170d2a32652ce31ca9e5 by sam.mccall [clangd] Disambiguate overloads of std::move for header insertion. Up until now, we relied on matching the filename. This depends on unstable details of libstdc++ and doesn't work well on other stdlibs. Also we'd like to remove it (see D88204). Differential Revision: https://reviews.llvm.org/D88885
	clang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
	clang-tools-extra/clangd/unittests/CanonicalIncludesTests.cpp
	clang-tools-extra/clangd/index/CanonicalIncludes.cpp
	clang-tools-extra/clangd/index/SymbolCollector.h
	clang-tools-extra/clangd/index/SymbolCollector.cpp
Commit e72cfd938f21bd194a2d2f45a4f8ee7d94d33bf8 by Amara Emerson Rename the VECREDUCE_STRICT_{FADD,FMUL} SDNodes to VECREDUCE_SEQ_{FADD,FMUL}. The STRICT was causing unnecessary confusion. I think SEQ is a more accurate name for what they actually do, and the other obvious option of "ORDERED" has the issue of already having a meaning in FP contexts. Differential Revision: https://reviews.llvm.org/D88791
	llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
	llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
	llvm/include/llvm/CodeGen/ISDOpcodes.h
Commit 7361ce73efcfba8ac12b7dc1f57a6291ea961c41 by Stanislav.Mekhanoshin [AMDGPU] Use default zero flag operands in flat scratch This is no-op so far because we do not select these yet. Differential Revision: https://reviews.llvm.org/D88920
	llvm/lib/Target/AMDGPU/FLATInstructions.td
Commit a73166a45204378f6f8b4a6ff2d962f0ff56d51e by flo [LAA] Use DL to get element size for bound computation. Currently LAA uses getScalarSizeInBits to compute the size of an element when computing the end bound of an access. This does not work as expected for pointers to pointers, because getScalarSizeInBits will return 0 for pointer types. By using DataLayout to get the size of the element we can also correctly handle pointer element types. Note the changes to the existing test, which seems to also use the wrong offset for the end. Fixes PR47751. Reviewed By: anemet Differential Revision: https://reviews.llvm.org/D88953
	llvm/test/Transforms/LoopVectorize/runtime-check-pointer-element-type.ll
	llvm/lib/Analysis/LoopAccessAnalysis.cpp
	llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
Commit dd2f79ed4422860ea9507e17cc33f1262d09db50 by hubert.reinterpretcast [test][MC] Use %python in llvm/test/MC/COFF/bigobj.py ... instead of the one on the $PATH. Reviewed By: hubert.reinterpretcast Differential Revision: https://reviews.llvm.org/D88986
	llvm/test/MC/COFF/bigobj.py
Commit 45014ce36f28698bb0e84ecad3a3ea7da4f476ad by Stanislav.Mekhanoshin [AMDGPU] Add tied operand to d16 scratch loads This is still no-op because there is no selection for these opcodes. Differential Revision: https://reviews.llvm.org/D88927
	llvm/lib/Target/AMDGPU/FLATInstructions.td
Commit c1247f0e74bff00ab9a896a8132318916f3e84a7 by Amara Emerson [mlir] Fix build after 322d0afd875df66b36e4810a2b95c20a8f22ab9b due to change in intrinsic overloads. I'd forgottent to run the mlir tests after removing the scalar input overload on the fadd/fmul reductions. This is a quick fix for the mlir bot.
	mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
	mlir/test/Target/llvmir-intrinsics.mlir