SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [AVR] Don't adjust for instruction size (details)
  2. [AVR] Decode single register instructions (details)
  3. [AVR] Disassemble multiplication instructions (details)
  4. [AVR] Disassemble instructions with fixed Z operand (details)
  5. [AVR] Disassemble double register instructions (details)
  6. [VectorCombine] do not use magic number for undef mask element; NFC (details)
  7. [InstCombine] add tests for integer reductions; NFC (details)
  8. [InstCombine] reassociate diff of sums into sum of diffs (details)
  9. [PowerPC][Power10] Implement VSX PCV Generate Operations in LLVM/Clang (details)
  10. Distinguish between template parameter substitutions that are forming (details)
  11. [mlir][mlir-rocm-runner] Remove compile-time warning. NFC. (details)
  12. Fix a corner case in vector.shape_cast when the trailing dimensions are of size 1. (details)
  13. Fix rejects-valid when referencing an implicit operator== from within a (details)
  14. [SDAG] Add new AssertAlign ISD node. (details)
  15. [InstCombine] Replace selects with Phis (details)
  16. [SROA] Teach SROA to perform no-op pointer conversion. (details)
  17. [libc] Match x86 long double NaN classification with that of the compiler. (details)
  18. [Triple] support macOS 11 os version number (details)
Commit ff4817ec2adb1e716051c286bcdc5ef4d1b32dd3 by aykevanlaethem
[AVR] Don't adjust for instruction size

I'm not entirely sure why this was ever needed, but when I remove both
adjustments all tests still pass.

This fixes a bug where a long branch (using the `jmp` instead of the
`rjmp` instruction) was incorrectly adjusted by 2 because it jumps to an
absolute address instead of a PC-relative address. I could have added
AVR::fixup_call to the list of exceptions, but it seemed more sensible
to me to just remove this code.

Differential Revision: https://reviews.llvm.org/D78459
The file was addedllvm/test/CodeGen/AVR/jmp-long.ll
The file was modifiedllvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
Commit 01c2209d518c7f19de7997ac29385c699a7ccd35 by aykevanlaethem
[AVR] Decode single register instructions

This is a set of instructions that take just a single register as an
operand, with no immediates. Because all instructions share the same
format, I haven't added exhaustive bit testing to all instructions but
just to the inc instruction.

Differential Revision: https://reviews.llvm.org/D81968
The file was modifiedllvm/test/MC/AVR/inst-dec.s
The file was modifiedllvm/test/MC/AVR/inst-com.s
The file was modifiedllvm/test/MC/AVR/inst-ror.s
The file was modifiedllvm/test/MC/AVR/inst-neg.s
The file was modifiedllvm/test/MC/AVR/inst-pop.s
The file was modifiedllvm/test/MC/AVR/inst-inc.s
The file was modifiedllvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
The file was modifiedllvm/lib/Target/AVR/AVRInstrFormats.td
The file was modifiedllvm/test/MC/AVR/inst-push.s
The file was modifiedllvm/test/MC/AVR/inst-asr.s
The file was modifiedllvm/test/MC/AVR/inst-lsr.s
The file was modifiedllvm/test/MC/AVR/inst-swap.s
Commit ec9efb856c6f3c764c921cee3900eab48f0fc076 by aykevanlaethem
[AVR] Disassemble multiplication instructions

These can often only use a limited range of registers, and apparently
need special decoding support.

Differential Revision: https://reviews.llvm.org/D81971
The file was modifiedllvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
The file was modifiedllvm/test/MC/AVR/inst-muls.s
The file was modifiedllvm/test/MC/AVR/inst-fmul.s
The file was modifiedllvm/lib/Target/AVR/AVRInstrFormats.td
The file was modifiedllvm/test/MC/AVR/inst-fmulsu.s
The file was modifiedllvm/test/MC/AVR/inst-fmuls.s
The file was modifiedllvm/test/MC/AVR/inst-mulsu.s
Commit 9f09c29f0158f59dad07bce11e67470c0399c259 by aykevanlaethem
[AVR] Disassemble instructions with fixed Z operand

Some instructions have a fixed Z register and don't have an explicit
register operand. This can be worked around by simply printing the
operand directly if the particular register class is detected.

The LPM and ELPM instructions also needed a custom decoder, which is
also included in this patch.

Differential Revision: https://reviews.llvm.org/D82088
The file was modifiedllvm/test/MC/AVR/inst-las.s
The file was modifiedllvm/test/MC/AVR/inst-xch.s
The file was modifiedllvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
The file was modifiedllvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
The file was modifiedllvm/test/MC/AVR/inst-spm.s
The file was modifiedllvm/test/MC/AVR/inst-lat.s
The file was modifiedllvm/test/MC/AVR/inst-elpm.s
The file was modifiedllvm/test/MC/AVR/inst-lac.s
The file was modifiedllvm/test/MC/AVR/inst-lpm.s
The file was modifiedllvm/lib/Target/AVR/AVRInstrFormats.td
Commit eac4a601548566fb311b0b596dbaee893507cfb8 by aykevanlaethem
[AVR] Disassemble double register instructions

Add disassembly support for the movw, adiw, and sbiw instructions.

I had previously committed test cases for the adiw and sbiw
instructions, but had accidentally made them not runnable so they were
skipped all this time. Oops. This patch fixes that by adding support for
disassembling those instructions.

Differential Revision: https://reviews.llvm.org/D82093
The file was modifiedllvm/lib/Target/AVR/AVRInstrFormats.td
The file was modifiedllvm/test/MC/AVR/inst-movw.s
The file was modifiedllvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
The file was modifiedllvm/test/MC/AVR/inst-adiw.s
The file was modifiedllvm/test/MC/AVR/inst-sbiw.s
Commit 54143e2bd557e97c5c9032ff87d73eec6fc63c67 by spatel
[VectorCombine] do not use magic number for undef mask element; NFC
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit 7e1f376f8016bcfea4067de28c42ec6a7eb091fe by spatel
[InstCombine] add tests for integer reductions; NFC
The file was modifiedllvm/test/Transforms/InstCombine/vector-reductions.ll
Commit 8953ecf22bcf665ffb06399a97265ab71aebebf8 by spatel
[InstCombine] reassociate diff of sums into sum of diffs

This is the integer sibling to D81491.

(a[0] + a[1] + a[2] + a[3]) - (b[0] + b[1] + b[2] +b[3]) -->
(a[0] - b[0]) + (a[1] - b[1]) + (a[2] - b[2]) + (a[3] - b[3])

Removing the "experimental" from these intrinsics is likely
not too far away.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modifiedllvm/test/Transforms/InstCombine/vector-reductions.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
Commit 19df9e2959cfa3f25d798bd842df798e2b75f1b2 by amy.kwan1
[PowerPC][Power10] Implement VSX PCV Generate Operations in LLVM/Clang

This patch implements builtins for the following prototypes for the VSX Permute
Control Vector Generate with Mask Instructions:

vector unsigned char vec_genpcvm (vector unsigned char, const int);
vector unsigned short vec_genpcvm (vector unsigned short, const int);
vector unsigned int vec_genpcvm (vector unsigned int, const int);
vector unsigned long long vec_genpcvm (vector unsigned long long, const int);

Differential Revision: https://reviews.llvm.org/D81774
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedllvm/test/MC/PowerPC/p10.s
The file was addedllvm/test/CodeGen/PowerPC/p10-vsx-pcv.ll
The file was modifiedllvm/test/MC/Disassembler/PowerPC/p10insts.txt
Commit 9f9373f86d2d13b8c9f106863ce70ace69abf388 by richard
Distinguish between template parameter substitutions that are forming
specializations and those that are done as part of rewrites.

Do not create Subst* nodes in the latter. We previously had a hybrid of
these two behaviors where we would only create some Subst* nodes but not
others during deduction guide rewrites.

No functional change intended, but the resulting ASTs are more
principled.
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
The file was modifiedclang/test/SemaTemplate/deduction-guide.cpp
The file was modifiedclang/include/clang/Sema/Template.h
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
Commit b7c4912996d65d54e129feed7bd44c7aa0ece508 by whchung
[mlir][mlir-rocm-runner] Remove compile-time warning. NFC.

Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, stephenneuendorffer, Joonsoo, grosul1, Kayjukh, jurahul, msifontes

Tags: #mlir

Differential Revision: https://reviews.llvm.org/D82333
The file was modifiedmlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp
Commit 6bb4fc93c2fd7f63c7ed430928d1b85bfd4b3d79 by whchung
Fix a corner case in vector.shape_cast when the trailing dimensions are of size 1.

Differential Revision: https://reviews.llvm.org/D82304
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
Commit 2a3b86c157166f3b15f718443334ab0e27b40592 by richard
Fix rejects-valid when referencing an implicit operator== from within a
templated class.

When a defaulted operator<=> results in the injection of a defaulted
operator==, that operator== can be named by unqualified name within the
same class, even if the class is templated. To make this work, perform
the transform from defaulted operator<=> to defaulted operator== in the
template definition context instead of the template instantiation
context.

This results in our substituting into a declaration from a context where
we don't have a full list of template arguments (or indeed any), for
which we are now more careful to not spuriously instantiate declarations
that are not dependent on the arguments we're substituting.
The file was modifiedclang/lib/AST/DeclBase.cpp
The file was modifiedclang/include/clang/Sema/Template.h
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
The file was addedclang/test/SemaTemplate/defaulted.cpp
The file was modifiedclang/test/PCH/cxx2a-defaulted-comparison.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/include/clang/AST/DeclBase.h
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
Commit b1360caa823d35ea3067eb6a1519014b4fd105eb by michael.hliao
[SDAG] Add new AssertAlign ISD node.

Summary:
- AssertAlign node records the guaranteed alignment on its source node,
  where these alignments are retrieved from alignment attributes in LLVM
  IR. These tracked alignments could help DAG combining and lowering
  generating efficient code.
- In this patch, the basic support of AssertAlign node is added. So far,
  we only generate AssertAlign nodes on return values from intrinsic
  calls.
- Addressing selection in AMDGPU is revised accordingly to capture the
  new (base + offset) patterns.

Reviewers: arsenm, bogner

Subscribers: jvesely, wdng, nhaehnle, tpr, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81711
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAG.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
Commit 9bff376e5c10ea384a6eee93f7d7668d670a66e7 by mkazantsev
[InstCombine] Replace selects with Phis

We can sometimes replace a select with a Phi node if all of its values
are available on respective incoming edges.

Differential Revision: https://reviews.llvm.org/D82005
Reviewed By: nikic
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/select.ll
Commit f95850ce9c7593d3d8d2f83c55197970f373b9ad by michael.hliao
[SROA] Teach SROA to perform no-op pointer conversion.

Summary:
- When promoting a pointer from memory to register, SROA skips pointers
  from different address spaces. However, as `ptrtoint` and `inttoptr`
  are defined as no-op casts if that integer type has the same as the
  pointer value, generate the pair of `ptrtoint`/`inttoptr` (no-op cast)
  sequence to convert pointers from different address spaces if they
  have the same size.

Reviewers: arsenm, chandlerc, lebedev.ri

Subscribers:

Differential Revision: https://reviews.llvm.org/D81943
The file was modifiedllvm/test/Transforms/SROA/non-integral-pointers.ll
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp
The file was modifiedllvm/test/Transforms/SROA/address-spaces.ll
The file was modifiedllvm/test/Transforms/SROA/alloca-address-space.ll
Commit 987fac79c9a951806cbda6b178b05fcb5145fde8 by sivachandra
[libc] Match x86 long double NaN classification with that of the compiler.

Reviewers: asteinhauser

Differential Revision: https://reviews.llvm.org/D82330
The file was addedlibc/test/utils/FPUtil/CMakeLists.txt
The file was addedlibc/test/utils/FPUtil/x86_long_double_test.cpp
The file was addedlibc/test/utils/CMakeLists.txt
The file was modifiedlibc/test/CMakeLists.txt
The file was modifiedlibc/utils/FPUtil/LongDoubleBitsX86.h
Commit 1c4a42a4d88eeca8de47d615a23fc654a39abdb7 by Alex Lorenz
[Triple] support macOS 11 os version number

macOS goes to 11! This commit adds support for the new version number by ensuring
that existing version comparison routines, and the 'darwin' OS identifier
understands the new numbering scheme. It also adds a new utility method
'getCanonicalVersionForOS', which lets users translate some uses of
macOS 10.16 into macOS 11. This utility method will be used in upcoming
clang and swift commits.

Differential Revision: https://reviews.llvm.org/D82337
The file was modifiedllvm/lib/Support/Triple.cpp
The file was modifiedllvm/unittests/ADT/TripleTest.cpp
The file was modifiedllvm/include/llvm/ADT/Triple.h