SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [RISCV] Assemble/Disassemble v-ext instructions. (details)
  2. [RISCV] Support experimental v extensions. (details)
  3. [X86] SimplifyDemandedVectorEltsForTargetNode - merge shuffle/pack lower demanded elements handling. (details)
  4. [ValueTracking] Use a switch statement (NFC) (details)
  5. [RISCV] Silence unused variable warning in Release builds. NFC. (details)
  6. [LIT] Correcting max-failures option in lit documentation. (details)
  7. Add OpenBSD support to be able to retrieve the thread id (details)
Commit 66da87dcbaf91fa3393ce80c687e9c2d133ee3ca by kai.wang
[RISCV] Assemble/Disassemble v-ext instructions.

Assemble/disassemble RISC-V V extension instructions according to
latest version spec in https://github.com/riscv/riscv-v-spec/.

I have tested this patch using GNU toolchain. The encoding is aligned
to GNU assembler output. In this patch, there is a test case for each
instruction at least.

The V register definition is just for assemble/disassemble. Its type
is not important in this stage. I think it will be reviewed and modified
as we want to do codegen for scalable vector types.

This patch does not include Zvamo, Zvlsseg, and Zvediv.

Differential revision: https://reviews.llvm.org/D69987
The file was addedllvm/test/MC/RISCV/rvv/fmul.s
The file was addedllvm/test/MC/RISCV/rvv/shift.s
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was addedllvm/test/MC/RISCV/rvv/sub.s
The file was modifiedllvm/lib/Target/RISCV/RISCV.td
The file was addedllvm/test/MC/RISCV/rvv/sign-injection.s
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
The file was addedllvm/test/MC/RISCV/rvv/vsetvl.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrFormats.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was addedllvm/test/MC/RISCV/rvv/mv.s
The file was addedllvm/test/MC/RISCV/rvv/and.s
The file was addedllvm/test/MC/RISCV/rvv/minmax.s
The file was addedllvm/test/MC/RISCV/rvv/macc.s
The file was addedllvm/test/MC/RISCV/rvv/compare.s
The file was addedllvm/test/MC/RISCV/rvv/fothers.s
The file was addedllvm/test/MC/RISCV/rvv/or.s
The file was addedllvm/test/MC/RISCV/rvv/div.s
The file was addedllvm/test/MC/RISCV/rvv/mul.s
The file was addedllvm/lib/Target/RISCV/RISCVInstrFormatsV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.td
The file was addedllvm/test/MC/RISCV/rvv/fmv.s
The file was addedllvm/test/MC/RISCV/rvv/xor.s
The file was modifiedllvm/lib/Target/RISCV/RISCVSystemOperands.td
The file was addedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
The file was addedllvm/test/MC/RISCV/rvv/add.s
The file was addedllvm/test/MC/RISCV/rvv/convert.s
The file was addedllvm/test/MC/RISCV/rvv/fdiv.s
The file was addedllvm/test/MC/RISCV/rvv/mask.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
The file was addedllvm/test/MC/RISCV/rvv/reduction.s
The file was addedllvm/test/MC/RISCV/rvv/clip.s
The file was addedllvm/test/MC/RISCV/rvv/fcompare.s
The file was addedllvm/test/MC/RISCV/rvv/fsub.s
The file was addedllvm/test/MC/RISCV/rvv/invalid.s
The file was addedllvm/test/MC/RISCV/rvv/fadd.s
The file was addedllvm/test/MC/RISCV/rvv/fminmax.s
The file was addedllvm/test/MC/RISCV/rvv/load.s
The file was addedllvm/test/MC/RISCV/rvv/others.s
The file was addedllvm/test/MC/RISCV/rvv/fmacc.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was addedllvm/test/MC/RISCV/rvv/store.s
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was addedllvm/test/MC/RISCV/rvv/freduction.s
The file was modifiedllvm/lib/Target/RISCV/RISCVSchedRocket32.td
The file was modifiedllvm/lib/Target/RISCV/RISCVSchedRocket64.td
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
The file was addedllvm/test/MC/RISCV/rvv/snippet.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
Commit d698ff92a59c0632aa6a88b72890eb401bd64faa by kai.wang
[RISCV] Support experimental v extensions.

This follows the design as discussed on the mailing lists in the
following RFC:
http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html

Support for the vector 'v' extension v0.8.

Differential revision: https://reviews.llvm.org/D81188
The file was modifiedclang/test/Driver/riscv-arch.c
The file was modifiedclang/lib/Driver/ToolChains/Arch/RISCV.cpp
Commit 393b4bd1362f6634a972157e7c2f3936f51f7356 by llvm-dev
[X86] SimplifyDemandedVectorEltsForTargetNode - merge shuffle/pack lower demanded elements handling.

Generalize the vector operand extraction code for shuffle/pack ops - we can assume that the vector operands are the same width as the result, and any non-vector values can be reused directly in the smaller width op.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 323cb26cef4a1766b660745c38238617c1f1cf33 by nikita.ppv
[ValueTracking] Use a switch statement (NFC)
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit 85b53598a984025afd96f2a00231ac6b0f20d7b2 by benny.kra
[RISCV] Silence unused variable warning in Release builds. NFC.
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit 8cd117c24f48428e01f88cf18480e5af7eb20c0c by Mike Edwards
[LIT] Correcting max-failures option in lit documentation.
The file was modifiedllvm/docs/CommandGuide/lit.rst
Commit 66b7ba52b7b49cb712c337b934440049ab94454b by brad
Add OpenBSD support to be able to retrieve the thread id
The file was modifiedllvm/lib/Support/Unix/Threading.inc