FailedChanges

Summary

  1. recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure separately in loop-vectorize In loop-vectorize, interleave count and vector factor depend on target register number. Currently, it does not estimate different register pressure for different register class separately(especially for scalar type, float type should not be on the same position with int type), so it's not accurate. Specifically, it causes too many times interleaving/unrolling, result in too many register spills in loop body and hurting performance. So we need classify the register classes in IR level, and importantly these are abstract register classes, and are not the target register class of backend provided in td file. It's used to establish the mapping between the types of IR values and the number of simultaneous live ranges to which we'd like to limit for some set of those types. For example, POWER target, register num is special when VSX is enabled. When VSX is enabled, the number of int scalar register is 32(GPR), float is 64(VSR), but for int and float vector register both are 64(VSR). So there should be 2 kinds of register class when vsx is enabled, and 3 kinds of register class when VSX is NOT enabled. It runs on POWER target, it makes big(+~30%) performance improvement in one specific bmk(503.bwaves_r) of spec2017 and no other obvious degressions. Differential revision: https://reviews.llvm.org/D67148
  2. [clang][IFS] Updating tests to pass on -fvisibility=hidden builds (NFCi). Special thanks to JamesNagurne who got to the bottom of this; landing this on his behalf. Differential Revision: https://reviews.llvm.org/D68897
Revision 374634 by wuzish:
recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure separately in loop-vectorize

In loop-vectorize, interleave count and vector factor depend on target register number. Currently, it does not
estimate different register pressure for different register class separately(especially for scalar type,
float type should not be on the same position with int type), so it's not accurate. Specifically,
it causes too many times interleaving/unrolling, result in too many register spills in loop body and hurting performance.

So we need classify the register classes in IR level, and importantly these are abstract register classes,
and are not the target register class of backend provided in td file. It's used to establish the mapping between
the types of IR values and the number of simultaneous live ranges to which we'd like to limit for some set of those types.

For example, POWER target, register num is special when VSX is enabled. When VSX is enabled, the number of int scalar register is 32(GPR),
float is 64(VSR), but for int and float vector register both are 64(VSR). So there should be 2 kinds of register class when vsx is enabled,
and 3 kinds of register class when VSX is NOT enabled.

It runs on POWER target, it makes big(+~30%) performance improvement in one specific bmk(503.bwaves_r) of spec2017 and no other obvious degressions.

Differential revision: https://reviews.llvm.org/D67148
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h (diff)llvm.src/include/llvm/Analysis/TargetTransformInfo.h
The file was modified/llvm/trunk/include/llvm/Analysis/TargetTransformInfoImpl.h (diff)llvm.src/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modified/llvm/trunk/include/llvm/CodeGen/BasicTTIImpl.h (diff)llvm.src/include/llvm/CodeGen/BasicTTIImpl.h
The file was modified/llvm/trunk/lib/Analysis/TargetTransformInfo.cpp (diff)llvm.src/lib/Analysis/TargetTransformInfo.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.h (diff)llvm.src/lib/Target/AArch64/AArch64TargetTransformInfo.h
The file was modified/llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.h (diff)llvm.src/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp (diff)llvm.src/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h (diff)llvm.src/lib/Target/PowerPC/PPCTargetTransformInfo.h
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp (diff)llvm.src/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.h (diff)llvm.src/lib/Target/SystemZ/SystemZTargetTransformInfo.h
The file was modified/llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp (diff)llvm.src/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
The file was modified/llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h (diff)llvm.src/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
The file was modified/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp (diff)llvm.src/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.h (diff)llvm.src/lib/Target/X86/X86TargetTransformInfo.h
The file was modified/llvm/trunk/lib/Target/XCore/XCoreTargetTransformInfo.h (diff)llvm.src/lib/Target/XCore/XCoreTargetTransformInfo.h
The file was modified/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (diff)llvm.src/lib/Transforms/Scalar/LoopStrengthReduce.cpp
The file was modified/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp (diff)llvm.src/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modified/llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff)llvm.src/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was added/llvm/trunk/test/Transforms/LoopVectorize/PowerPC/reg-usage.llllvm.src/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
The file was modified/llvm/trunk/test/Transforms/LoopVectorize/X86/reg-usage-debug.ll (diff)llvm.src/test/Transforms/LoopVectorize/X86/reg-usage-debug.ll
The file was modified/llvm/trunk/test/Transforms/LoopVectorize/X86/reg-usage.ll (diff)llvm.src/test/Transforms/LoopVectorize/X86/reg-usage.ll
Revision 374632 by zer0:
[clang][IFS] Updating tests to pass on -fvisibility=hidden builds (NFCi).

Special thanks to JamesNagurne who got to the bottom of this; landing this on
his behalf.

Differential Revision: https://reviews.llvm.org/D68897
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/test/InterfaceStubs/externstatic.c (diff)clang.src/test/InterfaceStubs/externstatic.c
The file was modified/cfe/trunk/test/InterfaceStubs/merge-conflict-test.c (diff)clang.src/test/InterfaceStubs/merge-conflict-test.c
The file was modified/cfe/trunk/test/InterfaceStubs/object-float.c (diff)clang.src/test/InterfaceStubs/object-float.c
The file was modified/cfe/trunk/test/InterfaceStubs/object.c (diff)clang.src/test/InterfaceStubs/object.c