Started 29 days ago
Took 18 hr on green-dragon-08

Failed Build #5545 (Oct 16, 2019 8:37:16 PM)

  • : 375076
  • : 375074
  • : 374977
  • : 364589
  • : 374854
  • : 375058
  1. Clang-formatting of some files in LiveRangeCalc header (LiveRangeCalc.h)

    NFC (detail/ViewSVN)
    by mggm
  2. Move LiveRangeCalc header to publicily available position. NFC

    Differential Revision: (detail/ViewSVN)
    by mggm
  3. Include sanitize blacklist and other extra deps as part of scan-deps output

    Clang's -M mode includes these extra dependencies in its output and clang-scan-deps
    should have equivalent behavior, so adding these extradeps to output just like
    how its being done for ".d" file generation mode.

    Reviewers: arphaman, dexonsmith, Bigcheese, jkorous

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by kousikk
  4. Correct placement of #ifndef NDEBUG in r375067 (detail/ViewSVN)
    by dsanders
  5. Fix unused variable in r375066 (detail/ViewSVN)
    by dsanders
  6. Revert Tag CFI-generated data structures with "#pragma clang section" attributes.

    This reverts r375022 (git commit e2692b3bc0327606748b6d291b9009d2c845ced5) (detail/ViewSVN)
    by dmikulin
  7. [gicombiner] Add the run-time rule disable option

    Each generated helper can be configured to generate an option that disables
    rules in that helper. This can be used to bisect rulesets.

    The disable bits are stored in a SparseVector as this is very cheap for the
    common case where nothing is disabled. It gets more expensive the more rules
    are disabled but you're generally doing that for debug purposes where
    performance is less of a concern.

    Depends on D68426

    Reviewers: volkan, bogner

    Reviewed By: volkan

    Subscribers: hiraditya, Petar.Avramovic, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by dsanders
  8. [GISel][CombinerHelper] Add concat_vectors(build_vector, build_vector) => build_vector

    Teach the combiner helper how to flatten concat_vectors of build_vectors
    into a build_vector.

    Add this combine as part of AArch64 pre-legalizer combiner.

    Differential Revision: (detail/ViewSVN)
    by qcolombet
  9. [lit] Improve lit.Run class

    * Push timing of overall test time into run module
    * Make lit.Run a proper class
    * Add a few TODO comments (detail/ViewSVN)
    by yln
  10. [Concepts] ConceptSpecializationExprs mangling

    Implement mangling for CSEs to match regular template-ids.
    Reviewed as part of D41569 <>.

    Re-commit fixing failing test. (detail/ViewSVN)
    by saar.raz
  11. [lit] Fix another test case that r374652 missed (detail/ViewSVN)
    by jdenny
  12. [gicombiner] Hoist pure C++ combine into the tablegen definition

    This is just moving the existing C++ code around and will be NFC w.r.t
    AArch64. Renamed 'CombineBr' to something more descriptive
    ('ElideByByInvertingCond') at the same time.

    The remaining combines in AArch64PreLegalizeCombiner require features that
    aren't implemented at this point and will be hoisted as they are added.

    Depends on D68424

    Reviewers: bogner, volkan

    Subscribers: kristof.beyls, hiraditya, Petar.Avramovic, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by dsanders
  13. [lit] Remove unnecessary usage of lit.Run (detail/ViewSVN)
    by yln
  14. [lit] Do not create semaphores when we do not need them

    Parallelism groups and semaphores are only required for parallel
    execution. (detail/ViewSVN)
    by yln
  15. [lit] Factor out separate methods for parallel and serial execution (detail/ViewSVN)
    by yln
  16. [NFC] Fix unused var in release builds (detail/ViewSVN)
    by rupprecht
  17. Revert [support] GlobPattern: add support for `\` and `[!...]`, and allow `]` in more places

    This reverts r375051 (git commit a409afaad64ce83ea44cc30ee5f96b6e613a6e98)

    The patch does not work on Windows due to `\` in filenames being interpreted as escaping rather than literal path separators when used by lld linker scripts. (detail/ViewSVN)
    by rupprecht
  18. [support] GlobPattern: add support for `\` and `[!...]`, and allow `]` in more places

    Summary: Update GlobPattern in libSupport to handle a few more cases. It does not fully match the `fnmatch` used by GNU objcopy since named character classes (e.g. `[[:digit:]]`) are not supported, but this should support most existing use cases (mostly just `*` is what's used anyway).

    This will be used to implement the `--wildcard` flag in llvm-objcopy to be more compatible with GNU objcopy.

    This is split off of D66613 to land the libSupport changes separately. The llvm-objcopy part will land soon.

    Reviewers: jhenderson, MaskRay, evgeny777, espindola, alexshap

    Reviewed By: MaskRay

    Subscribers: nickdesaulniers, emaste, arichardson, hiraditya, jakehehrlich, abrachet, seiya, llvm-commits

    Tags: #llvm

    Differential Revision:

    undo objcopy changes to make this libsupport only (detail/ViewSVN)
    by rupprecht
  19. [Utils] Cleanup similar cases to MergeBlockIntoPredecessor.

    There are two cases where a block is merged into its predecessor and the
    MergeBlockIntoPredecessor API is not used. Update the API so it can be
    reused in the other cases, in order to avoid code duplication.

    Cleanup motivated by D68659.

    Reviewers: chandlerc,, george.burgess.iv

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by asbirlea
  20. [lit] Print warning if we fail to delete temp directory (detail/ViewSVN)
    by yln
  21. [lit] Skip creation of tmp dir if we don't actually run any tests (detail/ViewSVN)
    by yln
  22. [lit] Remove return value from print_summary function (detail/ViewSVN)
    by yln
  23. [lit] Small refactoring and cleanups in

    * Remove outdated precautions for Python versions < 2.7
    * Remove dead code related to `maxIndividualTestTime` option
    * Move printing of test and result summary out of main into its own

    Reviewed By: rnk

    Differential Revision: (detail/ViewSVN)
    by yln
  24. Update ReleaseNotes: expand the section on enabling MemorySSA (detail/ViewSVN)
    by asbirlea
  25. [dsymutil] Print warning/error for unknown/missing arguments.

    After changing dsymutil to use libOption, we lost error reporting for
    missing required arguments (input files). Additionally, we stopped
    complaining about unknown arguments. This patch fixes both and adds a
    test. (detail/ViewSVN)
    by Jonas Devlieghere
  26. [AArch64] Fix offset calculation

    r374772 changed Offset to be an int64_t but left NewOffset as an int.
    Scale is unsigned, so in the calculation `Offset - NewOffset * Scale`,
    `NewOffset * Scale` was promoted to unsigned and was then zero-extended
    to 64 bits, leading to an incorrect computation which manifested as an
    out-of-memory when building the Swift standard library for Android
    aarch64. Promote NewOffset to int64_t to fix this, and promote
    EmittableOffset as well, since its one user passes it to a function
    which takes an int64_t anyway.

    Test case based on a suggestion by Sander de Smalen!

    Differential Revision: (detail/ViewSVN)
    by smeenai
  27. GlobalISel: Implement lower for G_SADDO/G_SSUBO

    Port directly from SelectionDAG, minus the path using
    by arsenm
  28. [Symbolize] Use the local MSVC C++ demangler instead of relying on dbghelp. NFC.

    This allows making a couple llvm-symbolizer tests run in all

    Differential Revision: (detail/ViewSVN)
    by mstorsjo
  29. Remove a stale comment, noted in post commit review for rL375038 (detail/ViewSVN)
    by reames
  30. [clangd] Add the missing dependency on `clangLex`. (detail/ViewSVN)
    by hliao
  31. [IndVars] Fix a miscompile in off-by-default loop predication implementation

    The problem is that we can have two loop exits, 'a' and 'b', where 'a' and 'b' would exit at the same iteration, 'a' precedes 'b' along some path, and 'b' is predicated while 'a' is not. In this case (see the previously submitted test case), we causing the loop to exit through 'b' whereas it should have exited through 'a'.

    This only applies to loop exits where the exit counts are not provably inequal, but that isn't as much of a restriction as it appears. If we could order the exit counts, we'd have already removed one of the two exits. In theory, we might be able to prove inequality w/o ordering, but I didn't really explore that piece. Instead, I went for the obvious restriction and ensured we didn't predicate exits following non-predicateable exits.

    Credit goes to Evgeny Brevnov for figuring out the problematic case. Fuzzing probably also found it (failures seen), but due to some silly infrastructure problems I hadn't gotten to the results before Evgeny hand reduced it from a benchmark (he manually enabled the transform). Once this is fixed, I'll try to filter through the fuzzer failures to see if there's anything additional lurking.

    Differential Revision (detail/ViewSVN)
    by reames
  32. [AMDGPU] Do not combine dpp mov reading physregs

    We cannot be sure physregs will stay unchanged.

    Differential Revision: (detail/ViewSVN)
    by rampitec
  33. Replace platform-dependent `stat` with `llvm::sys::fs::status`. NFC intended.

    Reviewers: bruno, sammccall

    Reviewed By: sammccall

    Subscribers: jkorous, dexonsmith, arphaman, ributzka, cfe-commits

    Differential Revision: (detail/ViewSVN)
    by vsapsai
  34. [AMDGPU] Do not combine dpp with physreg def

    We will remove dpp mov along with the physreg def otherwise.

    Differential Revision: (detail/ViewSVN)
    by rampitec
  35. [llvm-ar] Implement the V modifier as an alias for --version

    Summary: Also update the help modifier (h) so that it works as a modifier and not just as a standalone `h`. For example, `llvm-ar h` prints the help message, but `llvm-ar xh` currently prints `unknown option h`.

    Reviewers: MaskRay, gbreynoo

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by rupprecht
  36. Fix darwin-ld-lto test for some speical path

    Fix the test by not assuming the prefix path of the temp directory can
    be matched by a regex.

    rdar://problem/56259195 (detail/ViewSVN)
    by steven_wu
  37. [OPENMP]Allow priority clause in combined task-based directives.

    The expression of the priority clause must be captured in the combined
    task-based directives, like 'parallel master taskloop' directive. (detail/ViewSVN)
    by abataev
  38. [SLP] avoid reduction transform on patterns that the backend can load-combine (2nd try)

    The 1st attempt at this modified the cost model in a bad way to avoid the vectorization,
    but that caused problems for other users (the loop vectorizer) of the cost model.

    I don't see an ideal solution to these 2 related, potentially large, perf regressions:

    We decided that load combining was unsuitable for IR because it could obscure other
    optimizations in IR. So we removed the LoadCombiner pass and deferred to the backend.
    Therefore, preventing SLP from destroying load combine opportunities requires that it
    recognizes patterns that could be combined later, but not do the optimization itself (
    it's not a vector combine anyway, so it's probably out-of-scope for SLP).

    Here, we add a cost-independent bailout with a conservative pattern match for a
    multi-instruction sequence that can probably be reduced later.

    In the x86 tests shown (and discussed in more detail in the bug reports), SDAG combining
    will produce a single instruction on these tests like:

      movbe   rax, qword ptr [rdi]


      mov     rax, qword ptr [rdi]

    Not some (half) vector monstrosity as we currently do using SLP:

      vpmovzxbq       ymm0, dword ptr [rdi + 1] # ymm0 = mem[0],zero,zero,..
      vpsllvq ymm0, ymm0, ymmword ptr [rip + .LCPI0_0]
      movzx   eax, byte ptr [rdi]
      movzx   ecx, byte ptr [rdi + 5]
      shl     rcx, 40
      movzx   edx, byte ptr [rdi + 6]
      shl     rdx, 48
      or      rdx, rcx
      movzx   ecx, byte ptr [rdi + 7]
      shl     rcx, 56
      or      rcx, rdx
      or      rcx, rax
      vextracti128    xmm1, ymm0, 1
      vpor    xmm0, xmm0, xmm1
      vpshufd xmm1, xmm0, 78          # xmm1 = xmm0[2,3,0,1]
      vpor    xmm0, xmm0, xmm1
      vmovq   rax, xmm0
      or      rax, rcx

    Differential Revision: (detail/ViewSVN)
    by spatel
  39. [lit] Fix a test case that r374652 missed (detail/ViewSVN)
    by jdenny
  40. Tag CFI-generated data structures with "#pragma clang section" attributes.

    Differential Revision: (detail/ViewSVN)
    by dmikulin
  41. [NFC][XCOFF][AIX] Rename ControlSections to CsectGroup

    The name of ControlSections is not expressive enough to convey what they really are.
    CsectGroup can better communicate the concept of grouping csects together since they have similar property.

    Reviewer: daltenty

    Differential Revision: (detail/ViewSVN)
    by jasonliu
  42. [lit] Fix internal diff's --strip-trailing-cr and use it

    Using GNU diff, `--strip-trailing-cr` removes a `\r` appearing before
    a `\n` at the end of a line.  Without this patch, lit's internal diff
    only removes `\r` if it appears as the last character.  That seems
    useless.  This patch fixes that.

    This patch also adds `--strip-trailing-cr` to some tests that fail on
    Windows bots when D68664 is applied.  Based on what I see in the bot
    logs, I think the following is happening.  In each test there, lit
    diff is comparing a file with `\r\n` line endings to a file with `\n`
    line endings.  Without D68664, lit diff reads those files in text
    mode, which in Windows causes `\r\n` to be replaced with `\n`.
    However, with D68664, lit diff reads the files in binary mode instead
    and thus reports that every line is different, just as GNU diff does
    (at least under Ubuntu).  Adding `--strip-trailing-cr` to those tests
    restores the previous behavior while permitting the behavior of lit
    diff to be more like GNU diff.

    Reviewed By: rnk

    Differential Revision: (detail/ViewSVN)
    by jdenny
  43. CombinerHelper - silence dead assignment warnings. NFCI.

    Copy the NewAlignment value to Alignment first and then use that to update the stack frame object alignments. (detail/ViewSVN)
    by rksimon
  44. [lit] Clean up internal diff's encoding handling

    As suggested by rnk at D67643#1673043, instead of reading files
    multiple times until an appropriate encoding is found, read them once
    as binary, and then try to decode what was read.

    For Python >= 3.5, don't fail when attempting to decode the
    `diff_bytes` output in order to print it.

    Avoid failures for Python 2.7 used on some Windows bots by
    transforming diff output with `lit.util.to_string` before writing it
    to stdout.

    Finally, add some tests for encoding handling.

    Reviewed By: rnk

    Differential Revision: (detail/ViewSVN)
    by jdenny
  45. [OPENMP]Use different addresses for zeroed thread_id/bound_id.

    When the parallel region is called directly in the sequential region,
    the zeroed tid/bound id are used. But they must point to the different
    memory locations as the parameters are marked as noalias. (detail/ViewSVN)
    by abataev
  46. [AMDGPU] Supress unused sdwa insts generation

    Do not generate non-existing sdwa instructions. It reduces the
    number of generated instructions by 185.

    Differential Revision: (detail/ViewSVN)
    by rampitec
  47. [Remarks] Fix warning for ambigous `else` behind EXPECT macro (detail/ViewSVN)
    by thegameg
  48. [Remarks] Fix unit test by only checking for the path (detail/ViewSVN)
    by thegameg
  49. [SVE][IR] Small TypeSize improvements left out of initial commit

    The commit for D53137 left out the last round of improvements
    requested by reviewers. Adding those in now. (detail/ViewSVN)
    by huntergr
  50. [DWARF5] Added support for DW_AT_noreturn attribute to be emitted for
    C++ class member functions.

    Patch by Sourabh Singh Tomar!

    Differential Revision: (detail/ViewSVN)
    by Adrian Prantl
  51. [Remarks] Use StringRef::contains to avoid differences in error string

    Different OSs have different error strings: (detail/ViewSVN)
    by thegameg
  52. [AArch64,Assembler] Compiler support for ID_MMFR5_EL1

    Summary: Add read-only system register ID_MMFR5_EL1 and unit tests.

    Subscribers: kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by markrvmurray
  53. [Codegen] Adjust saturation test. NFC.

    Add some extra sat tests and adjust some of the existing tests to use signext where it would naturally be. (detail/ViewSVN)
    by dmgreen
  54. [Remarks] Add support for prepending a path to external files

    This helps with testing and debugging for paths that are assumed

    It also uses a FileError to provide the file path it's trying to open. (detail/ViewSVN)
    by thegameg
  55. bpf: fix wrong truncation elimination when there is back-edge/loop

    Currently, BPF backend is doing truncation elimination. If one truncation
    is performed on a value defined by narrow loads, then it could be redundant
    given BPF loads zero extend the destination register implicitly.

    When the definition of the truncated value is a merging value (PHI node)
    that could come from different code paths, then checks need to be done on
    all possible code paths.

    Above described optimization was introduced as r306685, however it doesn't
    work when there is back-edge, for example when loop is used inside BPF

    For example for the following code, a zero-extended value should be stored
    into b[i], but the "and reg, 0xffff" is wrongly eliminated which then
    generates corrupted data.

    void cal1(unsigned short *a, unsigned long *b, unsigned int k)
      unsigned short e;

      e = *a;
      for (unsigned int i = 0; i < k; i++) {
        b[i] = e;
        e = ~e;

    The reason is r306685 was trying to do the PHI node checks inside isel
    DAG2DAG phase, and the checks are done on MachineInstr. This is actually
    wrong, because MachineInstr is being built during isel phase and the
    associated information is not completed yet. A quick search shows none
    target other than BPF is access MachineInstr info during isel phase.

    For an PHI node, when you reached it during isel phase, it may have all
    predecessors linked, but not successors. It seems successors are linked to
    PHI node only when doing SelectionDAGISel::FinishBasicBlock and this
    happens later than PreprocessISelDAG hook.

    Previously, BPF program doesn't allow loop, there is probably the reason
    why this bug was not exposed.

    This patch therefore fixes the bug by the following approach:
    - The existing truncation elimination code and the associated
       "load_to_vreg_" records are removed.
    - Instead, implement truncation elimination using MachineSSA pass, this
       is where all information are built, and keep the pass together with other
       similar peephole optimizations inside BPFMIPeephole.cpp. Redundant move
       elimination logic is updated accordingly.
    - Unit testcase included + no compilation errors for kernel BPF selftest.

    Patch Review
    Patch was sent to and reviewed by BPF community at:

    Reported-by: David Beckett <>
    Reviewed-by: Yonghong Song <>
    Signed-off-by: Jiong Wang <> (detail/ViewSVN)
    by jiwang
  56. [RISCV] Add MachineInstr immediate verification

    This patch implements the `TargetInstrInfo::verifyInstruction` hook for RISC-V. Currently the hook verifies the machine instruction's immediate operands, to check if the immediates are within the expected bounds. Without the hook invalid immediates are not detected except when doing assembly parsing, so they are silently emitted (including being truncated when emitting object code).

    The bounds information is specified in tablegen by using the `OperandType` definition, which sets the `MCOperandInfo`'s `OperandType` field. Several RISC-V-specific immediate operand types were created, which extend the `MCInstrDesc`'s `OperandType` `enum`.

    To have the hook called with `llc` pass it the `-verify-machineinstrs` option. For Clang add the cmake build config `-DLLVM_ENABLE_EXPENSIVE_CHECKS=True`, or temporarily patch `TargetPassConfig::addVerifyPass`.

    Review concerns:

    - The patch adds immediate operand type checks that cover at least the base ISA. There are several other operand types for the C extension and one type for the F/D extensions that were left out of this initial patch because they introduced further design concerns that I felt were best evaluated separately.

    - Invalid register classes (e.g. passing a GPR register where a GPRC is expected) are already caught, so were not included.

    - This design makes the more abstract `MachineInstr` verification depend on MC layer definitions, which arguably is not the cleanest design, but is in line with how things are done in other parts of the target and LLVM in general.

    - There is some duplication of logic already present in the `MCOperandPredicate`s. Since the `MachineInstr` and `MCInstr` notions of immediates are fundamentally different, this is currently necessary.

    Reviewers: asb, lenary

    Reviewed By: lenary

    Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by luismarques
  57. [AMDGPU] Fix-up cases where writelane has 2 SGPR operands

    Even though writelane doesn't have the same constraints as other valu
    instructions it still can't violate the >1 SGPR operand constraint

    Due to later register propagation (e.g. fixing up vgpr operands via
    readfirstlane) changing writelane to only have a single SGPR is tricky.

    This implementation puts a new check after SIFixSGPRCopies that prevents
    multiple SGPRs being used in any writelane instructions.

    The algorithm used is to check for trivial copy prop of suitable constants into
    one of the SGPR operands and perform that if possible. If this isn't possible
    put an explicit copy of Src1 SGPR into M0 and use that instead (this is
    allowable for writelane as the constraint is for SGPR read-port and not
    constant-bus access).

    Reviewers: rampitec, tpr, arsenm, nhaehnle

    Reviewed By: rampitec, arsenm, nhaehnle

    Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, mgorny, yaxunl, tpr, t-tye, llvm-commits

    Tags: #llvm

    Differential Revision:

    Change-Id: Ic7553fa57440f208d4dbc4794fc24345d7e0e9ea (detail/ViewSVN)
    by dstuttard
  58. [libTooling] Fix r374962: add more Transformer forwarding decls.

    The move to a new, single namespace in r374962 left out some type definitions
    from the old namespace and resulted in one naming conflict (`text`).  This
    revision adds aliases for those definitions and removes one of the `text`
    functions from the new namespace.

    Reviewers: alexfh

    Subscribers: cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by ymandel
  59. [llvm-ar] Make paths case insensitive when on windows

    When on windows gnu-ar treats member names as case insensitive. This
    commit implements the same behaviour.

    Differential Revision: (detail/ViewSVN)
    by gbreynoo
  60. [Driver,ARM] Make -mfloat-abi=soft turn off MVE.

    Since `-mfloat-abi=soft` is taken to mean turning off all uses of the
    FP registers, it should turn off the MVE vector instructions as well
    as NEON and scalar FP. But it wasn't doing so.

    So the options `-march=armv8.1-m.main+mve.fp+fp.dp -mfloat-abi=soft`
    would cause the underlying LLVM to //not// support MVE (because it
    knows the real target feature relationships and turned off MVE when
    the `fpregs` feature was removed), but the clang layer still thought
    it //was// supported, and would misleadingly define the feature macro

    The ARM driver code already has a long list of feature names to turn
    off when `-mfloat-abi=soft` is selected. The fix is to add the missing
    entries `mve` and `mve.fp` to that list.

    Reviewers: dmgreen

    Subscribers: kristof.beyls, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by statham
  61. [Alignment][NFC] Optimize alignTo

    Summary: A small optimization suggested by jakehehrlich@ in D64790.

    Reviewers: jakehehrlich, courbet

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by gchatelet
  62. RedirectingFileSystem::openFileForRead - replace bitwise & with boolean && to fix warning

    Seems to be just a typo - now matches other instances which do something similar (detail/ViewSVN)
    by rksimon
  63. RealFile - fix self-initialization warning in constructor. (detail/ViewSVN)
    by rksimon
  64. [InstCombine][AMDGPU] Fix crash with v3i16/v3f16 buffer intrinsics

    This is something of a workaround to avoid a crash later on in type
    legalizer (WidenVectorResult()).
    Also added some f16 tests, including a non-working v3f16 case with
    a FIXME.

    Reviewers: arsenm, tpr, nhaehnle

    Reviewed By: arsenm

    Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by Piotr Sobczak
  65. Revert "[HardwareLoops] Optimisation remarks"

    while I investigate the PPC build bot failures.

    This reverts commit ad763751565b9663bc338fa2ca5ade86c6ca22ec. (detail/ViewSVN)
    by sjoerdmeijer
  66. RewriteModernObjC - silence static analyzer getAs<> null dereference warnings. NFCI.

    The static analyzer is warning about potential null dereferences, but in these cases we should be able to use castAs<> directly and if not assert will fire for us. (detail/ViewSVN)
    by rksimon
  67. [ARM] Add a register class for GPR pairs without SP and use it. NFCI

    Currently Thumb2InstrInfo.cpp uses a register class which is
    auto-generated by tablegen. Such approach is fragile because
    auto-generated classes might change when other register classes are
    added. For example, before
    we were using GPRPair_with_gsub_1_in_rGPRRegClass, but had to
    change it to GPRPair_with_gsub_1_in_GPRwithAPSRnospRegClass
    because the former class stopped being generated (this did not change
    the functionality though).

    This patch adds a register class consisting of even-odd GPR register
    pairs from (R0, R1) to (R10, R11), which excludes (R12, SP) and uses
    it in Thumb2InstrInfo.cpp instead of

    Reviewers: ostannard, simon_tatham, dmgreen, efriedma

    Reviewed By: simon_tatham

    Subscribers: kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by miyuki
  68. CGDebugInfo - silence static analyzer dyn_cast<> null dereference warnings. NFCI.

    The static analyzer is warning about potential null dereferences, but in these cases we should be able to use cast<> directly and if not assert will fire for us. (detail/ViewSVN)
    by rksimon
  69. CGExprConstant - silence static analyzer getAs<> null dereference warning. NFCI.

    The static analyzer is warning about a potential null dereference, but in these cases we should be able to use castAs<> directly and if not assert will fire for us. (detail/ViewSVN)
    by rksimon
  70. CGBuiltin - silence static analyzer getAs<> null dereference warnings. NFCI.

    The static analyzer is warning about potential null dereferences, but in these cases we should be able to use castAs<> directly and if not assert will fire for us. (detail/ViewSVN)
    by rksimon
  71. SimpleLoopUnswitch - fix uninitialized variable and null dereference warnings. NFCI. (detail/ViewSVN)
    by rksimon
  72. Revert 374967 "[Concepts] ConceptSpecializationExprs mangling"

    This reverts commit 5e34ad109ced8dbdea9500ee28180315b2aeba3d.

    The mangling test fails on Windows:

    It also fails on ppc64le:

    Also revert follow-up  374971 "Fix failing mangle-concept.cpp test."
    (it did not help on Win/ppc64le). (detail/ViewSVN)
    by nico
  73. [AMDGPU] Extend the SI Load/Store optimizer

    Extend the SI Load/Store optimizer to merge MIMG load instructions. Handle
    different flavours of image_load and image_sample instructions.

    When the instructions of the same subclass differ only in dmask, merge
    them and update dmask accordingly.

    Reviewers: nhaehnle

    Reviewed By: nhaehnle

    Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by Piotr Sobczak
  74. gn build: Merge r374982 (detail/ViewSVN)
    by gnsyncbot
  75. [clangd] Add RemoveUsingNamespace tweak.

    Removes the 'using namespace' under the cursor and qualifies all accesses in the current file.
      using namespace std;
      vector<int> foo(std::map<int, int>);
    Would become:
      std::vector<int> foo(std::map<int, int>);

    Subscribers: mgorny, ilya-biryukov, MaskRay, jkorous, mgrang, arphaman, kadircet, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by usaxena95
  76. [ARM][ParallelDSP] Change smlad insertion order

    Instead of inserting everything after the 'root' of the reduction,
    insert all instructions as close to their operands as possible. This
    can help reduce register pressure.

    Differential Revision: (detail/ViewSVN)
    by sam_parker

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18527
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18528
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18529
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18530
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18531
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18532
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18533
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18534
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18535
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18536
originally caused by:

Started by upstream project Clang Stage 2: cmake, R -g Tsan, using Stage 1 RA build number 18538
originally caused by:

This run spent:

  • 17 hr waiting;
  • 18 hr build duration;
  • 1 day 12 hr total from scheduled to completion.

Identified problems

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Indication 1

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