SuccessChanges

Summary

  1. [InstCombine] add tests for fpext+select+fptrunc; NFC (details)
  2. [DebugInfo] Re-apply two patches to MachineSink (details)
  3. [DebugInfo] Don't reorder DBG_VALUEs when sunk (details)
  4. [DebugInfo] Don't create multiple DBG_VALUEs when sinking (details)
  5. [InstCombine] add FMF guard to builder in fptrunc transform; NFC (details)
  6. [InstCombine] narrow select with FP casts (details)
  7. [AMDGPU][HIP] Improve opt-level handling (details)
Commit 403bb33a2e6a966b9dae203cf7845d6d0538e76b by spatel
[InstCombine] add tests for fpext+select+fptrunc; NFC
The file was modifiedllvm/test/Transforms/InstCombine/fptrunc.ll
Commit fca41001963cb473182c7b3b665ea1f03f94203a by jmorse+git
[DebugInfo] Re-apply two patches to MachineSink
These were:
* D58386 / f5e1b718a67 / reverted in d382a8a768b
* D58238 / ee50590e168 / reverted in a8db456b53a
Of which the latter has a performance regression tracked in PR43855,
fixed by D70672 / D70676, which will be committed atomically with this
reapplication.
Contains a minor difference to account for a change in the IsCopyInstr
signature.
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was addedllvm/test/DebugInfo/MIR/X86/machinesink.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir
The file was addedllvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
Commit e4cdd6263175f7289cfb61608944892d8c76b6ff by jmorse+git
[DebugInfo] Don't reorder DBG_VALUEs when sunk
Fix part of PR43855, resolving a problem that comes from the
reapplication in 001574938e5. If we have two DBG_VALUE insts in a block
that specify the location of the same variable, for example:
   %0 = someinst
  DBG_VALUE %0, !123, !DIExpression()
  %1 = anotherinst
  DBG_VALUE %1, !123, !DIExpression()
if %0 were to sink, the corresponding DBG_VALUE would sink too, past the
next DBG_VALUE, effectively re-ordering assignments. To fix this, I've
added a SeenDbgVars set recording what variable locations have been seen
in a block already (working bottom up), and now flag DBG_VALUEs that
would pass a later DBG_VALUE for the same variable.
NB, this only works for repeated DBG_VALUEs in the same basic block, the
general case involving control flow is much harder, which I've written
up in PR44117.
Differential revision: https://reviews.llvm.org/D70672
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was modifiedllvm/test/DebugInfo/MIR/X86/machinesink.mir
Commit 30e8f80fd5a43a213f8feb124846223b61218f30 by jmorse+git
[DebugInfo] Don't create multiple DBG_VALUEs when sinking
This patch addresses a performance problem reported in PR43855, and
present in the reapplication in in 001574938e5. It turns out that
MachineSink will (often) move instructions to the first block that
post-dominates the current block, and then try to sink further. This
means if we have a lot of conditionals, we can needlessly create large
numbers of DBG_VALUEs, one in each block the sunk instruction passes
through.
To fix this, rather than immediately sinking DBG_VALUEs, record them in
a pass structure. When sinking is complete and instructions won't be
sunk any further, new DBG_VALUEs are added, avoiding lots of
intermediate DBG_VALUE $noregs being created.
Differential revision: https://reviews.llvm.org/D70676
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
The file was modifiedllvm/test/DebugInfo/MIR/X86/machinesink.mir
Commit 51e420c27e2dc493bd71a6305ffb4d8acb401755 by spatel
[InstCombine] add FMF guard to builder in fptrunc transform; NFC
This makes no difference currently because we don't apply FMF to FP
casts, but that may change.
This could also be a place to add a fold for select with fptrunc, so it
will make that patch easier/smaller.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Commit 3c6b5d3674e85f2be81e74d104055269c017a430 by spatel
[InstCombine] narrow select with FP casts
Select doesn't change values, so truncate of extended operand cancels
out.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/fptrunc.ll
Commit d96ea47c75fdf4a62358eae49a0026bcf031bde6 by scott.linder
[AMDGPU][HIP] Improve opt-level handling
Summary: The HIP toolchain invokes `llc` without an explicit opt-level,
meaning it always uses the default (-O2). This makes it impossible to
use -O1, for example. The HIP toolchain also coerces -Os/-Oz to -O2 even
when invoking opt, and it coerces -Og to -O2 rather than -O1.
Forward the opt-level to `llc` as well as `opt`, and only coerce levels
where it is required.
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D70987
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
The file was modifiedclang/test/Driver/hip-toolchain-rdc.hip
The file was addedclang/test/Driver/hip-toolchain-opt.hip
The file was modifiedclang/test/Driver/hip-toolchain-mllvm.hip
The file was modifiedclang/test/Driver/hip-toolchain-no-rdc.hip