SuccessChanges

Summary

  1. [AutoFDO] Top-down Inlining for specialization with context-sensitive (details)
  2. Handle two corner cases in creduce-clang-crash.py (details)
  3. [RegisterCoalescer] Fix the creation of subranges when rematerialization (details)
  4. [ThinLTO] Add option to disable readonly/writeonly attribute propagation (details)
Commit 532196d811ad4db1e522012c9d20e4a95aae2eb3 by aktoon
[AutoFDO] Top-down Inlining for specialization with context-sensitive
profile
Summary: AutoFDO's sample profile loader processes function in arbitrary
source code order, so if I change the order of two functions in source
code, the inline decision can change. This also prevented the use of
context-sensitive profile to do specialization while inlining. This
commit enforces SCC top-down order for sample profile loader. With this
change, we can now do specialization, as illustrated by the added test
case:
Say if we have A->B->C and D->B->C call path, we want to inline C into B
when root inliner is B, but not when root inliner is A or D, this is not
possible without enforcing top-down order. E.g. Once C is inlined into
B, A and D can only choose to inline (B->C) as a whole or nothing, but
what we want is only inline B into A and D, not its recursive callee C.
If we process functions in top-down order, this is no longer a problem,
which is what this commit is doing.
This change is guarded with a new switch "-sample-profile-top-down-load"
for tuning, and it depends on D70653. Eventually, top-down can be the
default order for sample profile loader.
Reviewers: wmi, davidxl
Subscribers: hiraditya, llvm-commits, tejohnson
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70655
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
The file was addedllvm/test/Transforms/SampleProfile/inline-topdown.ll
The file was addedllvm/test/Transforms/SampleProfile/Inputs/inline-topdown.prof
Commit 1f822f212cde1ad9099cf45af0652a83380de772 by rnk
Handle two corner cases in creduce-clang-crash.py
Summary: First, call os.path.normpath on the filename argument. I passed
in
./foo-asdf.cpp, and this meant that the script failed to find the
filename, and bad things happened.
Second, call os.path.abspath on binaries. CReduce runs the
interestingness test in a temp dir, so relative paths will not work.
Reviewers: akhuang
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D71098
The file was modifiedclang/utils/creduce-clang-crash.py
Commit 2ec71ea7c74df20983031c6e1be07b14da0e9109 by qcolombet
[RegisterCoalescer] Fix the creation of subranges when rematerialization
is used
* Context *
During register coalescing, we use rematerialization when coalescing is
not possible. That means we may rematerialize a super register when only
a smaller register is actually used. E.g., 0B v1 = ldimm 0xFF 1B v2 =
COPY v1.low8bits 2B   = v2
=> 0B v1 = ldimm 0xFF 1B v2 = ldimm 0xFF 2B   = v2.low8bits
Where xB are the slot indexes. Here v2 grew from a 8-bit register to a
16-bit register.
When that happens and subregister liveness is enabled, we create
subranges for the newly created value. E.g., before remat, the live
range of v2 looked like: main range: [1r, 2r)
(Reads v2 is defined at index 1 slot register and used before the slot
register of index 2)
After remat, it should look like: main range: [1r, 2r) low 8 bits: [1r,
2r) high 8 bits: [1r, 1d) <-- dead def
I.e., the unsused lanes of v2 should be marked as dead definition.
* The Problem *
Prior to this patch, the live-ranges from the previous exampel, would
have the full live-range for all subranges: main range: [1r, 2r) low 8
bits: [1r, 2r) high 8 bits: [1r, 2r) <-- too long
* The Fix *
Technically, the code that this patch changes is not wrong: When we
create the subranges for the newly rematerialized value, we create only
one subrange for the whole bit mask. In other words, at this point v2
live-range looks like this: main range: [1r, 2r) low & high: [1r, 2r)
Then, it gets wrong when we call LiveInterval::refineSubRanges on low 8
bits: main range: [1r, 2r) low 8 bits: [1r, 2r) high 8 bits: [1r, 2r)
<-- too long
Ideally, we would like LiveInterval::refineSubRanges to be able to do
the right thing and mark the dead lanes as such. However, this is not
possible, because by the time we update / refine the live ranges, the IR
hasn't been updated yet, therefore we actually don't have enough
information to do the right thing.
Another option to fix the problem would have been to call
LiveIntervals::shrinkToUses after the IR is updated. This is not
desirable as this may have a noticeable impact on compile time.
Instead, what this patch does is when we create the subranges for the
rematerialized value, we explicitly create one subrange for the lanes
that were used before rematerialization and one for the lanes that were
not used. The used one inherits the live range of the main range and the
unused one is just created empty. The existing rematerialization code
then detects that the unused one are not live and it correctly sets dead
def intervals for them.
https://llvm.org/PR41372
The file was addedllvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
The file was modifiedllvm/lib/CodeGen/RegisterCoalescer.cpp
Commit 54a3c2a81e1a0ff970705008e9285ea3ada4ef3e by tejohnson
[ThinLTO] Add option to disable readonly/writeonly attribute propagation
Summary: Add an option to allow the attribute propagation on the index
to be disabled, to allow a workaround for issues (such as that fixed by
D70977).
Also move the setting of the WithAttributePropagation flag on the index
into propagateAttributes(), and remove some old stale code that predated
this flag and cleared the maybe read/write only bits when we need to
disable the propagation (previously only when importing disabled, now
also when the new option disables it).
Reviewers: evgeny777, steven_wu
Subscribers: mehdi_amini, inglorion, hiraditya, dexonsmith, arphaman,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70984
The file was modifiedllvm/lib/Transforms/IPO/FunctionImport.cpp
The file was modifiedllvm/test/ThinLTO/X86/writeonly.ll
The file was modifiedllvm/lib/IR/ModuleSummaryIndex.cpp