FailedChanges

Summary

  1. [IR] Split out target specific intrinsic enums into separate headers (details)
  2. [AArch64][SVE] Add patterns for scalable vselect (details)
Commit 5d986953c8b917bacfaa1f800fc1e242559f76be by rnk
[IR] Split out target specific intrinsic enums into separate headers
This has two main effects:
- Optimizes debug info size by saving 221.86 MB of obj file size in a
Windows optimized+debug build of 'all'. This is 3.03% of 7,332.7MB of
object file size.
- Incremental step towards decoupling target intrinsics.
The enums are still compact, so adding and removing a single
target-specific intrinsic will trigger a rebuild of all of LLVM.
Assigning distinct target id spaces is potential future work.
Part of PR34259
Reviewers: efriedma, echristo, MaskRay
Reviewed By: echristo, MaskRay
Differential Revision: https://reviews.llvm.org/D71320
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreISelLowering.cpp
The file was modifiedllvm/include/llvm/IR/Function.h
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/TableGen/intrinsic-long-name.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonGenExtract.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstructionSelector.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
The file was modifiedllvm/test/TableGen/intrinsic-struct.td
The file was modifiedllvm/lib/Target/NVPTX/NVVMReflect.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Analysis/ConstantFolding.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
The file was modifiedllvm/lib/Target/Mips/MipsInstructionSelector.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/ARM/ARMParallelDSP.cpp
The file was modifiedllvm/lib/IR/Function.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/R600ISelLowering.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
The file was modifiedllvm/lib/Target/X86/X86InstructionSelector.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsSEISelLowering.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/include/llvm/IR/Intrinsics.h
The file was modifiedllvm/lib/CodeGen/TypePromotion.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
The file was modifiedllvm/unittests/IR/IRBuilderTest.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
The file was modifiedllvm/include/llvm/IR/CMakeLists.txt
The file was modifiedllvm/lib/CodeGen/WasmEHPrepare.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVVMIntrRange.cpp
The file was modifiedllvm/lib/Target/X86/X86FastISel.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
The file was modifiedllvm/lib/Analysis/MemoryLocation.cpp
The file was modifiedllvm/lib/Target/Mips/MipsLegalizerInfo.cpp
The file was modifiedclang/lib/CodeGen/CGException.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/include/llvm/IR/CallSite.h
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was modifiedllvm/include/llvm/IR/GlobalValue.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/X86/X86WinEHState.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/X86/X86IntrinsicsInfo.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZTDC.cpp
The file was modifiedllvm/include/llvm/IR/InstrTypes.h
The file was modifiedllvm/lib/Target/AArch64/AArch64StackTagging.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp
Commit 7aa5c160885c92c95ad84216de9b9b02dbc95936 by mcinally
[AArch64][SVE] Add patterns for scalable vselect
This patch matches scalable vector selects to predicated move
instructions.
Differential Revision: https://reviews.llvm.org/D71298
The file was addedllvm/test/CodeGen/AArch64/sve-select.ll
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td