SuccessChanges

Summary

  1. [BPI] Adjust the probability for floating point unordered comparison Since NaN is very rare in normal programs, so the probability for floating point unordered comparison should be extremely small. Current probability is 3/8, it is too large, this patch changes it to a tiny number. Differential Revision: https://reviews.llvm.org/D65303
  2. AMDGPU/GlobalISel: Select G_FABS/G_FNEG f64 doesn't work yet because tablegen currently doesn't handlde REG_SEQUENCE. This does regress some multi use VALU fneg cases since now the immediate remains in an SGPR, and more moves are used for legalizing the xor. This is a SIFixSGPRCopies deficiency.
  3. AMDGPU/GlobalISel: Select cvt pk intrinsics
  4. AMDGPU/GlobalISel: Select llvm.amdgcn.sffbh
  5. [NFC][InstCombine][InstSimplify] PR43251 - and some patterns with offset != 0 https://rise4fun.com/Alive/21b
Revision 371541 by carrot:
[BPI] Adjust the probability for floating point unordered comparison

Since NaN is very rare in normal programs, so the probability for floating point unordered comparison should be extremely small. Current probability is 3/8, it is too large, this patch changes it to a tiny number.

Differential Revision: https://reviews.llvm.org/D65303
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (diff)llvm.src/lib/Analysis/BranchProbabilityInfo.cpp
The file was added/llvm/trunk/test/Analysis/BranchProbabilityInfo/fcmp.llllvm.src/test/Analysis/BranchProbabilityInfo/fcmp.ll
The file was modified/llvm/trunk/test/CodeGen/SystemZ/call-05.ll (diff)llvm.src/test/CodeGen/SystemZ/call-05.ll
Revision 371540 by arsenm:
AMDGPU/GlobalISel: Select G_FABS/G_FNEG

f64 doesn't work yet because tablegen currently doesn't handlde
REG_SEQUENCE.

This does regress some multi use VALU fneg cases since now the
immediate remains in an SGPR, and more moves are used for legalizing
the xor. This is a SIFixSGPRCopies deficiency.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SIInstructions.td
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/fneg-combines.ll (diff)llvm.src/test/CodeGen/AMDGPU/fneg-combines.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/fneg.ll (diff)llvm.src/test/CodeGen/AMDGPU/fneg.ll
Revision 371539 by arsenm:
AMDGPU/GlobalISel: Select cvt pk intrinsics
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td (diff)llvm.src/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.td (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
Revision 371538 by arsenm:
AMDGPU/GlobalISel: Select llvm.amdgcn.sffbh
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.td (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td (diff)llvm.src/lib/Target/AMDGPU/VOP1Instructions.td
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mirllvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
Revision 371537 by lebedevri:
[NFC][InstCombine][InstSimplify] PR43251 - and some patterns with offset != 0

https://rise4fun.com/Alive/21b
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll (diff)llvm.src/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
The file was added/llvm/trunk/test/Transforms/InstSimplify/result-of-usub-by-nonzero-is-non-zero-and-no-overflow.llllvm.src/test/Transforms/InstSimplify/result-of-usub-by-nonzero-is-non-zero-and-no-overflow.ll