SuccessChanges

Summary

  1. [analyzer] Fix the 'analyzer-enabled-checkers.c' test on non-linux machines. '-Xclang -triple' doesn't seem to override the default target triple as reliably as '--target'. This leads to test failing due to platform-specific checks getting unexpectedly enabled.
  2. [AArch64][GlobalISel] Support sibling calls with outgoing arguments This adds support for lowering sibling calls with outgoing arguments. e.g ``` define void @foo(i32 %a) ``` Support is ported from AArch64ISelLowering's `isEligibleForTailCallOptimization`. The only thing that is missing is a full port of `TargetLowering::parametersInCSRMatch`. So, if we're using swiftself, we'll never tail call. - Rename `analyzeCallResult` to `analyzeArgInfo`, since the function is now used for both outgoing and incoming arguments - Teach `OutgoingArgHandler` about tail calls. Tail calls use frame indices for stack arguments. - Teach `lowerFormalArguments` to set the bytes in the caller's stack argument area. This is used later to check if the tail call's parameters will fit on the caller's stack. - Add `areCalleeOutgoingArgsTailCallable` to perform the eligibility check on the callee's outgoing arguments. For testing: - Update call-translator-tail-call to verify that we can now tail call with outgoing arguments, use G_FRAME_INDEX for stack arguments, and respect the size of the caller's stack - Remove GISel-specific check lines from speculation-hardening.ll, since GISel now tail calls like the other selectors - Add a GISel test line to tailcall-string-rvo.ll since we can tail call in that test now - Add a GISel test line to tailcall_misched_graph.ll since we tail call there now. Add specific check lines for GISel, since the debug output from the machine-scheduler differs with GlobalISel. The dependency still holds, but the output comes out in a different order. Differential Revision: https://reviews.llvm.org/D67471
  3. [PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC register class. Summary: Since the SPE4RC register class contains an identical set of registers and an identical spill size to the GPRC class its slightly confusing the tablegen emitter. It's preventing the GPRC_and_GPRC_NOR0 synthesized register class from inheriting VTs and AltOrders from GPRC or GPRC_NOR0. This is because SPE4C is found first in the super register class list when inheriting these properties and it doesn't set the VTs or AltOrders the same way as GPRC or GPRC_NOR0. This patch replaces all uses of GPE4RC with GPRC and allows GPRC and GPRC_NOR0 to contain f32. The test changes here are because the AltOrders are being inherited to GPRC_NOR0 now. Found while trying to determine if getCommonSubClass needs to take a VT argument. It was originally added to support fp128 on x86-64, I've changed some things about that so that it might be needed anymore. But a PowerPC test crashed without it and I think its due to this subclass issue. Reviewers: jhibbits, nemanjai, kbarton, hfinkel Subscribers: wuzish, nemanjai, mehdi_amini, hiraditya, kbarton, MaskRay, dexonsmith, jsji, shchenz, steven.zhang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67513
  4. Remove a duplicate test Turns out I'd already added exactly the same test under the name non_unit_stride.
  5. [SCEV] Add smin support to getRangeRef We were failing to compute trip counts (both exact and maximum) for any loop which involved a comparison against either an umin or smin. It looks like this simply got missed when we added smin/umin to SCEV. (Note: umin was submitted separately earlier today. Turned out two folks hit this at the same time.) Differential Revision: https://reviews.llvm.org/D67514
Revision 371781 by dergachev:
[analyzer] Fix the 'analyzer-enabled-checkers.c' test on non-linux machines.

'-Xclang -triple' doesn't seem to override the default target triple
as reliably as '--target'. This leads to test failing due to
platform-specific checks getting unexpectedly enabled.
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/test/Analysis/analyzer-enabled-checkers.c (diff)clang.src/test/Analysis/analyzer-enabled-checkers.c
Revision 371780 by paquette:
[AArch64][GlobalISel] Support sibling calls with outgoing arguments

This adds support for lowering sibling calls with outgoing arguments.

e.g

```
define void @foo(i32 %a)
```

Support is ported from AArch64ISelLowering's `isEligibleForTailCallOptimization`.
The only thing that is missing is a full port of
`TargetLowering::parametersInCSRMatch`. So, if we're using swiftself,
we'll never tail call.

- Rename `analyzeCallResult` to `analyzeArgInfo`, since the function is now used
  for both outgoing and incoming arguments
- Teach `OutgoingArgHandler` about tail calls. Tail calls use frame indices for
  stack arguments.
- Teach `lowerFormalArguments` to set the bytes in the caller's stack argument
  area. This is used later to check if the tail call's parameters will fit on
  the caller's stack.
- Add `areCalleeOutgoingArgsTailCallable` to perform the eligibility check on
  the callee's outgoing arguments.

For testing:

- Update call-translator-tail-call to verify that we can now tail call with
  outgoing arguments, use G_FRAME_INDEX for stack arguments, and respect the
  size of the caller's stack
- Remove GISel-specific check lines from speculation-hardening.ll, since GISel
  now tail calls like the other selectors
- Add a GISel test line to tailcall-string-rvo.ll since we can tail call in that
  test now
- Add a GISel test line to tailcall_misched_graph.ll since we tail call there
  now. Add specific check lines for GISel, since the debug output from the
  machine-scheduler differs with GlobalISel. The dependency still holds, but
  the output comes out in a different order.

Differential Revision: https://reviews.llvm.org/D67471
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.h (diff)llvm.src/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpp (diff)llvm.src/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp (diff)llvm.src/lib/Target/AArch64/AArch64CallLowering.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.h (diff)llvm.src/lib/Target/AArch64/AArch64CallLowering.h
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll (diff)llvm.src/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/arm64-call-tailcalls.ll (diff)llvm.src/test/CodeGen/AArch64/arm64-call-tailcalls.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/speculation-hardening.ll (diff)llvm.src/test/CodeGen/AArch64/speculation-hardening.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/tailcall-string-rvo.ll (diff)llvm.src/test/CodeGen/AArch64/tailcall-string-rvo.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/tailcall_misched_graph.ll (diff)llvm.src/test/CodeGen/AArch64/tailcall_misched_graph.ll
Revision 371779 by ctopper:
[PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC register class.

Summary:
Since the SPE4RC register class contains an identical set of registers
and an identical spill size to the GPRC class its slightly confusing
the tablegen emitter. It's preventing the GPRC_and_GPRC_NOR0 synthesized
register class from inheriting VTs and AltOrders from GPRC or GPRC_NOR0.
This is because SPE4C is found first in the super register class list
when inheriting these properties and it doesn't set the VTs or
AltOrders the same way as GPRC or GPRC_NOR0.

This patch replaces all uses of GPE4RC with GPRC and allows GPRC and
GPRC_NOR0 to contain f32.

The test changes here are because the AltOrders are being inherited
to GPRC_NOR0 now.

Found while trying to determine if getCommonSubClass needs to take
a VT argument. It was originally added to support fp128 on x86-64,
I've changed some things about that so that it might be needed
anymore. But a PowerPC test crashed without it and I think its
due to this subclass issue.

Reviewers: jhibbits, nemanjai, kbarton, hfinkel

Subscribers: wuzish, nemanjai, mehdi_amini, hiraditya, kbarton, MaskRay, dexonsmith, jsji, shchenz, steven.zhang, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67513
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (diff)llvm.src/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (diff)llvm.src/lib/Target/PowerPC/PPCFastISel.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (diff)llvm.src/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (diff)llvm.src/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (diff)llvm.src/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (diff)llvm.src/lib/Target/PowerPC/PPCInstrInfo.td
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (diff)llvm.src/lib/Target/PowerPC/PPCRegisterInfo.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (diff)llvm.src/lib/Target/PowerPC/PPCRegisterInfo.td
The file was modified/llvm/trunk/test/CodeGen/PowerPC/inc-of-add.ll (diff)llvm.src/test/CodeGen/PowerPC/inc-of-add.ll
The file was modified/llvm/trunk/test/CodeGen/PowerPC/sub-of-not.ll (diff)llvm.src/test/CodeGen/PowerPC/sub-of-not.ll
Revision 371777 by reames:
Remove a duplicate test

Turns out I'd already added exactly the same test under the name non_unit_stride.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/LoopVectorize/X86/load-deref-pred.ll (diff)llvm.src/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
Revision 371776 by reames:
[SCEV] Add smin support to getRangeRef

We were failing to compute trip counts (both exact and maximum) for any loop which involved a comparison against either an umin or smin. It looks like this simply got missed when we added smin/umin to SCEV.  (Note: umin was submitted separately earlier today.  Turned out two folks hit this at the same time.)

Differential Revision: https://reviews.llvm.org/D67514
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/ScalarEvolution.cpp (diff)llvm.src/lib/Analysis/ScalarEvolution.cpp
The file was modified/llvm/trunk/test/Analysis/ScalarEvolution/max-expr-cache.ll (diff)llvm.src/test/Analysis/ScalarEvolution/max-expr-cache.ll
The file was modified/llvm/trunk/test/Analysis/ScalarEvolution/trip-count15.ll (diff)llvm.src/test/Analysis/ScalarEvolution/trip-count15.ll
The file was modified/llvm/trunk/test/Transforms/IRCE/rc-negative-bound.ll (diff)llvm.src/test/Transforms/IRCE/rc-negative-bound.ll