FailedChanges

Summary

  1. GSYM: add encoding and decoding to FunctionInfo This patch adds encoding and decoding of the FunctionInfo objects along with full error handling and tests. Full details of the FunctionInfo encoding format appear in the FunctionInfo.h header file. Differential Revision: https://reviews.llvm.org/D67506
  2. [ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores We were previously using the SelectT2AddrModeImm7 for both normal and narrowing MVE loads/stores. As the narrowing instructions do not accept sp as a register, it makes little sense to optimise a FrameIndex into the load, only to have to recover that later on. This adds a SelectTAddrModeImm7 which does not do that folding, and uses it for narrowing load/store patterns. Differential Revision: https://reviews.llvm.org/D67489
  3. [ARM] Fixup pipeline test. NFC
  4. [ARM] Reserve an emergency spill slot for fp16 addressing modes that need it Similar to D67327, but this time for the FP16 VLDR and VSTR instructions that use the AddrMode5FP16 addressing mode. We need to reserve an emergency spill slot for instructions that will be out of range to use sp directly. AddrMode5FP16 is 8 bits with a scale of 2. Differential Revision: https://reviews.llvm.org/D67483
Revision 372135 by gclayton:
GSYM: add encoding and decoding to FunctionInfo

This patch adds encoding and decoding of the FunctionInfo objects along with full error handling and tests. Full details of the FunctionInfo encoding format appear in the FunctionInfo.h header file.

Differential Revision: https://reviews.llvm.org/D67506
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/DebugInfo/GSYM/FunctionInfo.h (diff)llvm.src/include/llvm/DebugInfo/GSYM/FunctionInfo.h
The file was modified/llvm/trunk/lib/DebugInfo/GSYM/FunctionInfo.cpp (diff)llvm.src/lib/DebugInfo/GSYM/FunctionInfo.cpp
The file was modified/llvm/trunk/unittests/DebugInfo/GSYM/GSYMTest.cpp (diff)llvm.src/unittests/DebugInfo/GSYM/GSYMTest.cpp
Revision 372134 by dmgreen:
[ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores

We were previously using the SelectT2AddrModeImm7 for both normal and narrowing
MVE loads/stores. As the narrowing instructions do not accept sp as a register,
it makes little sense to optimise a FrameIndex into the load, only to have to
recover that later on. This adds a SelectTAddrModeImm7 which does not do that
folding, and uses it for narrowing load/store patterns.

Differential Revision: https://reviews.llvm.org/D67489
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (diff)llvm.src/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (diff)llvm.src/lib/Target/ARM/ARMInstrMVE.td
The file was modified/llvm/trunk/test/CodeGen/Thumb2/mve-stack.ll (diff)llvm.src/test/CodeGen/Thumb2/mve-stack.ll
Revision 372133 by dmgreen:
[ARM] Fixup pipeline test. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/ARM/O3-pipeline.ll (diff)llvm.src/test/CodeGen/ARM/O3-pipeline.ll
Revision 372132 by dmgreen:
[ARM] Reserve an emergency spill slot for fp16 addressing modes that need it

Similar to D67327, but this time for the FP16 VLDR and VSTR instructions that
use the AddrMode5FP16 addressing mode. We need to reserve an emergency spill
slot for instructions that will be out of range to use sp directly.
AddrMode5FP16 is 8 bits with a scale of 2.

Differential Revision: https://reviews.llvm.org/D67483
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (diff)llvm.src/lib/Target/ARM/ARMFrameLowering.cpp
The file was added/llvm/trunk/test/CodeGen/Thumb2/fp16-stacksplot.mirllvm.src/test/CodeGen/Thumb2/fp16-stacksplot.mir