SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Fix RegBankSelect G_SMULH/G_UMULH pre-gfx9 The scalar versions were only introduced in gfx9.
  2. GlobalISel: Don't materialize immarg arguments to intrinsics Encode them directly as an imm argument to G_INTRINSIC*. Since now intrinsics can now define what parameters are required to be immediates, avoid using registers for them. Intrinsics could potentially want a constant that isn't a legal register type. Also, since G_CONSTANT is subject to CSE and legalization, transforms could potentially obscure the value (and create extra work for the selector). The register bank of a G_CONSTANT is also meaningful, so this could throw off future folding and legalization logic for AMDGPU. This will be much more convenient to work with than needing to call getConstantVRegVal and checking if it may have failed for every constant intrinsic parameter. AMDGPU has quite a lot of intrinsics wth immarg operands, many of which need inspection during lowering. Having to find the value in a register is going to add a lot of boilerplate and waste compile time. SelectionDAG has always provided TargetConstant for constants which should not be legalized or materialized in a register. The distinction between Constant and TargetConstant was somewhat fuzzy, and there was no automatic way to force usage of TargetConstant for certain intrinsic parameters. They were both ultimately ConstantSDNode, and it was inconsistently used. It was quite easy to mis-select an instruction requiring an immediate. For SelectionDAG, start emitting TargetConstant for these arguments, and using timm to match them. Most of the work here is to cleanup target handling of constants. Some targets process intrinsics through intermediate custom nodes, which need to preserve TargetConstant usage to match the intrinsic expectation. Pattern inputs now need to distinguish whether a constant is merely compatible with an operand or whether it is mandatory. The GlobalISelEmitter needs to treat timm as a special case of a leaf node, simlar to MachineBasicBlock operands. This should also enable handling of patterns for some G_* instructions with immediates, like G_FENCE or G_EXTRACT. This does include a workaround for a crash in GlobalISelEmitter when ARM tries to uses "imm" in an output with a "timm" pattern source.
  3. gn build: Merge r372282
  4. llvm-reduce: Add pass to reduce instructions Patch by Diego Treviño! Differential Revision: https://reviews.llvm.org/D66263
  5. Initialize all fields in ABIArgInfo. Due to usage of an uninitialized fields, we end up with a Conditional jump or move depends on uninitialised value Fixes https://bugs.llvm.org/show_bug.cgi?id=40547 Commited on behalf of Martin Liska <mliska@suse.cz>
Revision 372286 by arsenm:
AMDGPU/GlobalISel: Fix RegBankSelect G_SMULH/G_UMULH pre-gfx9

The scalar versions were only introduced in gfx9.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (diff)llvm.src/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
Revision 372285 by arsenm:
GlobalISel: Don't materialize immarg arguments to intrinsics

Encode them directly as an imm argument to G_INTRINSIC*.

Since now intrinsics can now define what parameters are required to be
immediates, avoid using registers for them. Intrinsics could
potentially want a constant that isn't a legal register type. Also,
since G_CONSTANT is subject to CSE and legalization, transforms could
potentially obscure the value (and create extra work for the
selector). The register bank of a G_CONSTANT is also meaningful, so
this could throw off future folding and legalization logic for AMDGPU.

This will be much more convenient to work with than needing to call
getConstantVRegVal and checking if it may have failed for every
constant intrinsic parameter. AMDGPU has quite a lot of intrinsics wth
immarg operands, many of which need inspection during lowering. Having
to find the value in a register is going to add a lot of boilerplate
and waste compile time.

SelectionDAG has always provided TargetConstant for constants which
should not be legalized or materialized in a register. The distinction
between Constant and TargetConstant was somewhat fuzzy, and there was
no automatic way to force usage of TargetConstant for certain
intrinsic parameters. They were both ultimately ConstantSDNode, and it
was inconsistently used. It was quite easy to mis-select an
instruction requiring an immediate. For SelectionDAG, start emitting
TargetConstant for these arguments, and using timm to match them.

Most of the work here is to cleanup target handling of constants. Some
targets process intrinsics through intermediate custom nodes, which
need to preserve TargetConstant usage to match the intrinsic
expectation. Pattern inputs now need to distinguish whether a constant
is merely compatible with an operand or whether it is mandatory.

The GlobalISelEmitter needs to treat timm as a special case of a leaf
node, simlar to MachineBasicBlock operands. This should also enable
handling of patterns for some G_* instructions with immediates, like
G_FENCE or G_EXTRACT.

This does include a workaround for a crash in GlobalISelEmitter when
ARM tries to uses "imm" in an output with a "timm" pattern source.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h (diff)llvm.src/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h (diff)llvm.src/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modified/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (diff)llvm.src/include/llvm/Target/TargetSelectionDAG.td
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (diff)llvm.src/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (diff)llvm.src/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (diff)llvm.src/lib/Target/AArch64/AArch64InstrFormats.td
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (diff)llvm.src/lib/Target/AArch64/AArch64InstrInfo.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td (diff)llvm.src/lib/Target/AMDGPU/BUFInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/DSInstructions.td (diff)llvm.src/lib/Target/AMDGPU/DSInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (diff)llvm.src/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SIInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (diff)llvm.src/lib/Target/AMDGPU/SOPInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td (diff)llvm.src/lib/Target/AMDGPU/VOP1Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (diff)llvm.src/lib/Target/AMDGPU/VOP3Instructions.td
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (diff)llvm.src/lib/Target/ARM/ARMISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (diff)llvm.src/lib/Target/ARM/ARMInstrInfo.td
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (diff)llvm.src/lib/Target/ARM/ARMInstrThumb2.td
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td (diff)llvm.src/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td (diff)llvm.src/lib/Target/Hexagon/HexagonDepOperands.td
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td (diff)llvm.src/lib/Target/Hexagon/HexagonIntrinsics.td
The file was modified/llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td (diff)llvm.src/lib/Target/Mips/MicroMipsDSPInstrInfo.td
The file was modified/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (diff)llvm.src/lib/Target/Mips/Mips64InstrInfo.td
The file was modified/llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td (diff)llvm.src/lib/Target/Mips/MipsDSPInstrInfo.td
The file was modified/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (diff)llvm.src/lib/Target/Mips/MipsInstrInfo.td
The file was modified/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (diff)llvm.src/lib/Target/Mips/MipsMSAInstrInfo.td
The file was modified/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (diff)llvm.src/lib/Target/Mips/MipsSEISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (diff)llvm.src/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (diff)llvm.src/lib/Target/PowerPC/PPCInstrVSX.td
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td (diff)llvm.src/lib/Target/RISCV/RISCVInstrInfoA.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (diff)llvm.src/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (diff)llvm.src/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (diff)llvm.src/lib/Target/SystemZ/SystemZInstrFormats.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZInstrVector.td (diff)llvm.src/lib/Target/SystemZ/SystemZInstrVector.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZOperands.td (diff)llvm.src/lib/Target/SystemZ/SystemZOperands.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZOperators.td (diff)llvm.src/lib/Target/SystemZ/SystemZOperators.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZPatterns.td (diff)llvm.src/lib/Target/SystemZ/SystemZPatterns.td
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp (diff)llvm.src/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
The file was modified/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td (diff)llvm.src/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (diff)llvm.src/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.td (diff)llvm.src/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrMMX.td (diff)llvm.src/lib/Target/X86/X86InstrMMX.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.td (diff)llvm.src/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSystem.td (diff)llvm.src/lib/Target/X86/X86InstrSystem.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrTSX.td (diff)llvm.src/lib/Target/X86/X86InstrTSX.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrXOP.td (diff)llvm.src/lib/Target/X86/X86InstrXOP.td
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (diff)llvm.src/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.llllvm.src/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir (diff)llvm.src/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
The file was added/llvm/trunk/test/TableGen/immarg.tdllvm.src/test/TableGen/immarg.td
The file was modified/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp (diff)llvm.src/utils/TableGen/GlobalISelEmitter.cpp
Revision 372283 by gnsyncbot:
gn build: Merge r372282
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn (diff)llvm.src/utils/gn/secondary/llvm/tools/llvm-reduce/BUILD.gn
Revision 372282 by dblaikie:
llvm-reduce: Add pass to reduce instructions

Patch by Diego Treviño!

Differential Revision: https://reviews.llvm.org/D66263
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Reduce/Inputs/remove-bbs.py (diff)llvm.src/test/Reduce/Inputs/remove-bbs.py
The file was modified/llvm/trunk/test/Reduce/Inputs/remove-global-vars.py (diff)llvm.src/test/Reduce/Inputs/remove-global-vars.py
The file was added/llvm/trunk/test/Reduce/Inputs/remove-instructions.pyllvm.src/test/Reduce/Inputs/remove-instructions.py
The file was modified/llvm/trunk/test/Reduce/remove-global-vars.ll (diff)llvm.src/test/Reduce/remove-global-vars.ll
The file was added/llvm/trunk/test/Reduce/remove-instructions.llllvm.src/test/Reduce/remove-instructions.ll
The file was modified/llvm/trunk/tools/llvm-reduce/CMakeLists.txt (diff)llvm.src/tools/llvm-reduce/CMakeLists.txt
The file was modified/llvm/trunk/tools/llvm-reduce/DeltaManager.h (diff)llvm.src/tools/llvm-reduce/DeltaManager.h
The file was added/llvm/trunk/tools/llvm-reduce/deltas/ReduceInstructions.cppllvm.src/tools/llvm-reduce/deltas/ReduceInstructions.cpp
The file was added/llvm/trunk/tools/llvm-reduce/deltas/ReduceInstructions.hllvm.src/tools/llvm-reduce/deltas/ReduceInstructions.h
Revision 372281 by serge_sans_paille:
Initialize all fields in ABIArgInfo.

Due to usage of an uninitialized fields, we end up with
a Conditional jump or move depends on uninitialised value

Fixes https://bugs.llvm.org/show_bug.cgi?id=40547

Commited on behalf of Martin Liska <mliska@suse.cz>
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/include/clang/CodeGen/CGFunctionInfo.h (diff)clang.src/include/clang/CodeGen/CGFunctionInfo.h