SuccessChanges

Summary

  1. Use llvm::StringLiteral instead of StringRef in few places
  2. [CUDA][HIP] Fix hostness of defaulted constructor Clang does not respect the explicit device host attributes of defaulted special members. Also clang does not respect the hostness of special members determined by their first declarations. Clang also adds duplicate implicit device or host attributes in certain cases. This patch fixes that. Differential Revision: https://reviews.llvm.org/D67509
  3. [SLPVectorizer] add tests for bogus reductions; NFC https://bugs.llvm.org/show_bug.cgi?id=42708 https://bugs.llvm.org/show_bug.cgi?id=43146
  4. [Testing] Python 3 requires `print` to use parens
  5. [RISCV] Fix static analysis issues Unlikely to be problematic but still worth fixing. Differential Revision: https://reviews.llvm.org/D67640
  6. [Alignment][NFC] migrate DataLayout internal struct to llvm::Align Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 With this patch the PointerAlignElem struct goes from 20B to 16B. Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67400
  7. [FastISel] Fix insertion of unconditional branches during FastISel The insertion of an unconditional branch during FastISel can differ depending on building with or without debug information. This happens because FastISel::fastEmitBranch emits an unconditional branch depending on the size of the current basic block without distinguishing between debug and non-debug instructions. This patch fixes this issue by ignoring debug instructions when getting the size of the basic block. Reviewers: aprantl Reviewed By: aprantl Subscribers: ormris, aprantl, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67703
Revision 372395 by maskray:
Use llvm::StringLiteral instead of StringRef in few places
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp (diff)llvm.src/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (diff)llvm.src/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InsertPrefetch.cpp (diff)llvm.src/lib/Target/X86/X86InsertPrefetch.cpp
Revision 372394 by yaxunl:
[CUDA][HIP] Fix hostness of defaulted constructor
Clang does not respect the explicit device host attributes of defaulted special members.
Also clang does not respect the hostness of special members determined by their
first declarations.
Clang also adds duplicate implicit device or host attributes in certain cases.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D67509
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Sema/SemaCUDA.cpp (diff)clang.src/lib/Sema/SemaCUDA.cpp
The file was added/cfe/trunk/test/SemaCUDA/default-ctor.cuclang.src/test/SemaCUDA/default-ctor.cu
Revision 372393 by spatel:
[SLPVectorizer] add tests for bogus reductions; NFC

https://bugs.llvm.org/show_bug.cgi?id=42708
https://bugs.llvm.org/show_bug.cgi?id=43146
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/Transforms/SLPVectorizer/X86/bad-reduction.llllvm.src/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
Revision 372392 by davezarzycki:
[Testing] Python 3 requires `print` to use parens
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Reduce/Inputs/remove-instructions.py (diff)llvm.src/test/Reduce/Inputs/remove-instructions.py
Revision 372391 by luismarques:
[RISCV] Fix static analysis issues

Unlikely to be problematic but still worth fixing.

Differential Revision: https://reviews.llvm.org/D67640
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (diff)llvm.src/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (diff)llvm.src/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (diff)llvm.src/lib/Target/RISCV/RISCVISelLowering.cpp
Revision 372390 by gchatelet:
[Alignment][NFC] migrate DataLayout internal struct to llvm::Align

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

With this patch the PointerAlignElem struct goes from 20B to 16B.

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67400
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/DataLayout.h (diff)llvm.src/include/llvm/IR/DataLayout.h
The file was modified/llvm/trunk/lib/IR/DataLayout.cpp (diff)llvm.src/lib/IR/DataLayout.cpp
Revision 372389 by tellenbach:
[FastISel] Fix insertion of unconditional branches during FastISel

The insertion of an unconditional branch during FastISel can differ depending on
building with or without debug information. This happens because FastISel::fastEmitBranch
emits an unconditional branch depending on the size of the current basic block
without distinguishing between debug and non-debug instructions.

This patch fixes this issue by ignoring debug instructions when getting the size
of the basic block.

Reviewers: aprantl

Reviewed By: aprantl

Subscribers: ormris, aprantl, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67703
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/BasicBlock.h (diff)llvm.src/include/llvm/IR/BasicBlock.h
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (diff)llvm.src/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was modified/llvm/trunk/lib/IR/BasicBlock.cpp (diff)llvm.src/lib/IR/BasicBlock.cpp
The file was added/llvm/trunk/test/CodeGen/AArch64/fast-isel-branch-uncond-debug.llllvm.src/test/CodeGen/AArch64/fast-isel-branch-uncond-debug.ll
The file was modified/llvm/trunk/unittests/IR/BasicBlockTest.cpp (diff)llvm.src/unittests/IR/BasicBlockTest.cpp