1. [Codegen] Alter the default promotion for saturating adds and subs (details)
  2. Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" (details)
  3. Fix MSVC "not all control paths return a value" warning. NFCI. (details)
  4. [X86] Regenerate memcmp tests and add X64-AVX512 common prefix (details)
  5. [AArch64] Don't combine callee-save and local stack adjustment when (details)
  6. [LLD] [COFF] Try to report source locations for duplicate symbols (details)
  7. [ThinLTOCodeGenerator] Add support for index-based WPD (details)
  8. [Arm][libsanitizer] Fix arm libsanitizer failure with bleeding edge (details)
  9. SystemInitializerCommon fix compilation on linux (details)
  10. [AArch64][SVE] Add SPLAT_VECTOR ISD Node (details)
Commit e6f313b3807d23017d188aa7060b8cad09b3d095 by david.green
[Codegen] Alter the default promotion for saturating adds and subs
The default promotion for the add_sat/sub_sat nodes currently does:
   ANY_EXTEND iN to iM
   SHL by M-N
   L/ASHR by M-N
If the promoted add_sat or sub_sat node is not legal, this can produce
code that effectively does a lot of shifting (and requiring large
constants to be materialised) just to use the overflow flag. It is
simpler to just do the saturation manually, using the higher bitwidth
addition and a min/max against the saturating bounds. That is what this
patch attempts to do.
Differential Revision: https://reviews.llvm.org/D68926
llvm-svn: 375211
The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/usub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/X86/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/usub_sat.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/usub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/X86/uadd_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/usub_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/uadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/usub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/X86/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/X86/uadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/X86/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/X86/usub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat.ll
The file was modifiedllvm/test/CodeGen/X86/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/X86/usub_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/uadd_sat.ll
Commit da40d4e4e1bfa705dbf59ebce097ed34b0e46dfc by llvm-dev
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits"
warnings. NFCI.
llvm-svn: 375213
The file was modifiedllvm/lib/Object/MachOUniversal.cpp
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
Commit 3bd61b26556027a23b0d161d403f07fd7387ac77 by llvm-dev
Fix MSVC "not all control paths return a value" warning. NFCI.
llvm-svn: 375214
The file was modifiedllvm/tools/llvm-objcopy/CopyConfig.cpp
Commit ef04598e147396e7225964ae8438ecbf6554b095 by llvm-dev
[X86] Regenerate memcmp tests and add X64-AVX512 common prefix
Should help make the changes in D69157 clearer
llvm-svn: 375215
The file was modifiedllvm/test/CodeGen/X86/memcmp.ll
Commit 651f07908a149b8eb861a1b109f98eeb3d4f1517 by david.green
[AArch64] Don't combine callee-save and local stack adjustment when
optimizing for size
For arm64, D18619 introduced the ability to combine bumping the stack
pointer upfront in case it needs to be bumped for both the callee-save
area as well as the local stack area.
That diff already remarks that "This change can cause an increase in
instructions", but argues that even when that happens, it should be
still be a performance benefit because the number of micro-ops is
We have observed that this code-size increase can be significant in
practice. This diff disables combining stack bumping for methods that
are marked as optimize-for-size.
Example of a prologue with the behavior before this diff (combining
stack bumping when possible):
sub        sp, sp, #0x40
stp        d9, d8, [sp, #0x10]
stp        x20, x19, [sp, #0x20]
stp        x29, x30, [sp, #0x30]
add        x29, sp, #0x30
[... compute x8 somehow ...]
stp        x0, x8, [sp]
And after this  diff, if the method is marked as optimize-for-size:
stp        d9, d8, [sp, #-0x30]!
stp        x20, x19, [sp, #0x10]
stp        x29, x30, [sp, #0x20]
add        x29, sp, #0x20
[... compute x8 somehow ...]
stp        x0, x8, [sp, #-0x10]!
Note that without combining the stack bump there are two
auto-decrements, nicely folded into the stp instructions, whereas
otherwise there is a single sub sp, ... instruction, but not folded.
Patch by Nikolai Tillmann!
Differential Revision: https://reviews.llvm.org/D68530
llvm-svn: 375217
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/arm64-never-combine-csr-local-stack-bump-for-size.ll
Commit b38f577c015c210605c2e463e9ac6a03249225a2 by martin
[LLD] [COFF] Try to report source locations for duplicate symbols
This fixes the second part of PR42407.
For files with dwarf debug info, it manually loads and iterates
.debug_info to find the declared location of variables, to allow
reporting them. (This matches the corresponding code in the ELF linker.)
For functions, it uses the existing getFileLineDwarf which uses
LLVMSymbolizer for translating addresses to file lines.
In object files with codeview debug info, only the source location of
duplicate functions is printed. (And even there, only for the first
input file. The getFileLineCodeView function requires the object file to
be fully loaded and initialized to properly resolve source locations,
but duplicate symbols are reported at a stage when the second object
file isn't fully loaded yet.)
Differential Revision: https://reviews.llvm.org/D68975
llvm-svn: 375218
The file was modifiedlld/COFF/InputFiles.h
The file was modifiedlld/test/COFF/conflict-mangled.test
The file was modifiedlld/test/COFF/duplicate.test
The file was modifiedlld/COFF/SymbolTable.cpp
The file was modifiedlld/COFF/SymbolTable.h
The file was addedlld/test/COFF/duplicate-dwarf.s
The file was addedlld/test/COFF/duplicate-cv.s
The file was modifiedlld/test/COFF/conflict.test
The file was modifiedlld/COFF/InputFiles.cpp
Commit eb34c3e8a4a8311a4df5f13b217275e7c1985dc8 by eleviant
[ThinLTOCodeGenerator] Add support for index-based WPD
Differential revision: https://reviews.llvm.org/D68950
llvm-svn: 375219
The file was addedllvm/test/ThinLTO/X86/devirt_promote_legacy.ll
The file was modifiedllvm/lib/LTO/ThinLTOCodeGenerator.cpp
Commit 9c155985f17fd369bbba311b714fb6c01c17d66e by sjoerd.meijer
[Arm][libsanitizer] Fix arm libsanitizer failure with bleeding edge
Glibc has recently introduced changed to the mode field in ipc_perm in
commit 2f959dfe849e0646e27403f2e4091536496ac0f0. For Arm this means that
the mode field no longer has the same size.
This causes an assert failure against libsanitizer's internal copy of
ipc_perm. Since this change can't be easily detected I am adding arm to
the list of targets that are excluded from this check.
Patch by: Tamar Christina
Differential Revision: https://reviews.llvm.org/D69104
llvm-svn: 375220
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
Commit 0c304917740228968d2daf1a414e7ec3f94cd171 by pavel
SystemInitializerCommon fix compilation on linux
C++ defines two overloads of std::iscntrl. One in <cctype> and one in
<locale>. On linux we seem to include both which makes the std::erase_if
call ambiguous.
Wrap std::iscntrl call in a lambda to ensure regular overload
llvm-svn: 375221
The file was modifiedlldb/source/Initialization/SystemInitializerCommon.cpp
Commit 84da2596f96d388e9cd21d16e64687bca68f436a by graham.hunter
Adds a new ISD node to replicate a scalar value across all elements of a
vector. This is needed for scalable vectors, since BUILD_VECTOR cannot
be used.
Fixes up default type legalization for scalable vectors after the new
MVT type ranges were introduced.
At present I only use this node for scalable vectors. A DAGCombine has
been added to transform a BUILD_VECTOR into a SPLAT_VECTOR if all
elements are the same, but only if the default operation action of
Expand has been overridden by the target.
I've only added result promotion legalization for scalable vector
i8/i16/i32/i64 types in AArch64 for now.
Reviewers: t.p.northover, javed.absar, greened, cameron.mcinally,
Reviewed By: jmolloy
Differential Revision: https://reviews.llvm.org/D47775
llvm-svn: 375222
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was addedllvm/test/CodeGen/AArch64/sve-vector-splat.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp