FailedChanges

Summary

  1. [InstCombine] Fold uadd.sat(a, b) == 0 and usub.sat(a, b) == 0 (details)
  2. Reverted r375254 as it has broken some build bots for a long time. (details)
  3. gn build: Merge r375375 (details)
  4. [NFC][InstCombine] conditional sign-extend of high-bit-extract: 'and' (details)
  5. [InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern. (details)
Commit b1b7a2f7b63db915fbc0e7ee5e1811b8846fbd9b by nikita.ppv
[InstCombine] Fold uadd.sat(a, b) == 0 and usub.sat(a, b) == 0
This adds folds for comparing uadd.sat/usub.sat with zero:
* uadd.sat(a, b) == 0 => a == 0 && b == 0 => (a | b) == 0
* usub.sat(a, b) == 0 => a <= b
And inverted forms for !=.
Differential Revision: https://reviews.llvm.org/D69224
llvm-svn: 375374
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/Transforms/InstCombine/saturating-add-sub.ll
Commit 92c96c7bc0b456cbc32da97df52b1acec238be9f by vvereschaka
Reverted r375254 as it has broken some build bots for a long time.
llvm-svn: 375375
The file was modifiedllvm/lib/Transforms/Utils/SizeOpts.cpp
The file was removedllvm/unittests/CodeGen/MachineSizeOptsTest.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
The file was modifiedllvm/include/llvm/Transforms/Utils/SizeOpts.h
The file was removedllvm/lib/CodeGen/MachineSizeOpts.cpp
The file was modifiedllvm/lib/CodeGen/MachineLoopInfo.cpp
The file was removedllvm/include/llvm/CodeGen/MachineSizeOpts.h
The file was removedllvm/unittests/Transforms/Utils/SizeOptsTest.cpp
The file was modifiedllvm/lib/CodeGen/MachineDominators.cpp
The file was modifiedllvm/unittests/CodeGen/CMakeLists.txt
The file was modifiedllvm/include/llvm/CodeGen/MachineLoopInfo.h
The file was modifiedllvm/include/llvm/CodeGen/MachineDominators.h
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was modifiedllvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
The file was modifiedllvm/unittests/Transforms/Utils/CMakeLists.txt
Commit b01c077a1853a94168b83074fdd5fcf0d670104a by llvmgnsyncbot
gn build: Merge r375375
llvm-svn: 375376
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
Commit f7aec25d4fb193c2efb5c8bdcecd6d0611183bcc by lebedev.ri
[NFC][InstCombine] conditional sign-extend of high-bit-extract: 'and'
pat. can be 'or' pattern.
In this pattern, all the "magic" bits that we'd add are all high sign
bits, and in the value we'd be adding to they are all unset, not
unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups
llvm-svn: 375377
The file was modifiedllvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
Commit 7015a5c54b53d8d2297a3aa38bc32aab167bdcfc by lebedev.ri
[InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.
In this pattern, all the "magic" bits that we'd `add` are all high sign
bits, and in the value we'd be adding to they are all unset, not
unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups
It is possible that `haveNoCommonBitsSet()` should be taught about this
pattern so that we never have an `add` variant, but the reasoning would
need to be recursive (because of that `select`), so i'm not really sure
that would be worth it just yet.
llvm-svn: 375378
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modifiedllvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h