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Summary

  1. [MachineVerifier]  Improve checks of target instructions operands. (details)
Commit 4fd8f11901b5bfb13a5fef597626dde31835873b by paulsson
[MachineVerifier]  Improve checks of target instructions operands.
While working with a patch for instruction selection, the splitting of a
large immediate ended up begin treated incorrectly by the backend. Where
a register operand should have been created, it instead became an
immediate. To my surprise the machine verifier failed to report this,
which at the time would have been helpful.
This patch improves the verifier so that it will report this type of
error.
This patch XFAILs CodeGen/SPARC/fp128.ll, which has been reported at
https://bugs.llvm.org/show_bug.cgi?id=44091
Review: thegameg, arsenm, fhahn https://reviews.llvm.org/D63973
The file was modifiedllvm/test/CodeGen/SPARC/fp128.ll
The file was addedllvm/test/MachineVerifier/verify-regops.mir
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp