UnstableChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [ARM,MVE] Add an InstCombine rule permitting VPNOT. (details)
  2. [ARM,MVE] Rename and clean up VCTP IR intrinsics. (details)
  3. [ARM,MVE] Add intrinsics to deal with predicates. (details)
  4. Add AIX assembler support (details)
Commit 01aefae4a173c32a0235feb9600beffbcd0308b4 by simon.tatham
[ARM,MVE] Add an InstCombine rule permitting VPNOT.
Summary: If a user writing C code using the ACLE MVE intrinsics
generates a predicate and then complements it, then the resulting IR
will use the
`pred_v2i` IR intrinsic to turn some `<n x i1>` vector into a 16-bit
integer; complement that integer; and convert back. This will generate
machine code that moves the predicate out of the `P0` register,
complements it in an integer GPR, and moves it back in again.
This InstCombine rule replaces `i2v(~v2i(x))` with a direct complement
of the original predicate vector, which we can already instruction-
select as the VPNOT instruction which complements P0 in place.
Reviewers: ostannard, MarkMurrayARM, dmgreen
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70484
The file was modifiedllvm/test/Transforms/InstCombine/ARM/mve-v2i2v.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-from-intrinsics.ll
Commit 48cce077efcc3c3637aac0143b3c2c9d1cf7ab8b by simon.tatham
[ARM,MVE] Rename and clean up VCTP IR intrinsics.
Summary: D65884 added a set of Arm IR intrinsics for the MVE VCTP
instruction, to use in tail predication. But the 64-bit one doesn't work
properly: its predicate type is `<2 x i1>` / `v2i1`, which isn't a legal
MVE type (due to not having a full set of instructions that manipulate
it usefully). The test of `vctp64` in `basic-tail-pred.ll` goes through
`opt` fine, as the test expects, but if you then feed it to `llc` it
causes a type legality failure at isel time.
The usual workaround we've been using in the rest of the MVE intrinsics
family is to bodge `v2i1` into `v4i1`. So I've adjusted the
`vctp64` IR intrinsic to do that, and completely removed the code (and
test) that uses that intrinsic for 64-bit tail predication. That will
allow me to add isel rules (upcoming in D70485) that actually generate
the VCTP64 instruction.
Also renamed all four of these IR intrinsics so that they have `mve` in
the name, since its absence was confusing.
Reviewers: ostannard, MarkMurrayARM, dmgreen
Reviewed By: MarkMurrayARM
Subscribers: samparker, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70592
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-widen.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-from-intrinsics.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vctp.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-reduce-mve-tail.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-reduce.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit d173fb5d2854a1ce42bcc34832db5039b2c60e69 by simon.tatham
[ARM,MVE] Add intrinsics to deal with predicates.
Summary: This commit adds the `vpselq` intrinsics which take an MVE
predicate word and select lanes from two vectors; the `vctp` intrinsics
which create a tail predicate word suitable for processing the first m
elements of a vector (e.g. in the last iteration of a loop); and
`vpnot`, which simply complements a predicate word and is just syntactic
sugar for the `~` operator.
The `vctp` ACLE intrinsics are lowered to the IR intrinsics we've
already added (and which D70592 just reorganized). I've filled in the
missing isel rule for VCTP64, and added another set of rules to generate
the predicated forms.
I needed one small tweak in MveEmitter to allow the `unpromoted` type
modifier to apply to predicates as well as integers, so that `vpnot`
doesn't pointlessly convert its input integer to an `<n x i1>` before
complementing it.
Reviewers: ostannard, MarkMurrayARM, dmgreen
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D70485
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was addedclang/test/CodeGen/arm-mve-intrinsics/predicates.c
The file was addedllvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedclang/utils/TableGen/MveEmitter.cpp
Commit 3ebfab709583cfa7635693b123e56f76a1de765b by daltenty
Add AIX assembler support
Summary: A skeleton of AIX toolchain and system linker support has been
introduced in D68340, and this is a follow on patch to it. This patch
adds support to system assembler invocation to the AIX toolchain.
Reviewers: daltenty, hubert.reinterpretcast, jasonliu, Xiangling_L, dlj
Reviewed By: daltenty, hubert.reinterpretcast
Subscribers: wuzish, nemanjai, kbarton, jfb, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69620
The file was modifiedclang/lib/Driver/ToolChains/AIX.cpp
The file was addedclang/test/Driver/aix-as.c
The file was modifiedclang/lib/Driver/ToolChains/AIX.h
The file was addedclang/test/Driver/Inputs/aix_ppc_tree/dummy2.s
The file was addedclang/test/Driver/Inputs/aix_ppc_tree/dummy0.s
The file was addedclang/test/Driver/Inputs/aix_ppc_tree/dummy1.s