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Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. Revert r368276 "[TargetLowering] SimplifyDemandedBits - call (details)
  2. [ELF] Don't special case symbolic relocations with 0 addend to ifunc in (details)
Commit 5390d25f2b5cd6a9b234e30269661d7019a9850e by hans
Revert r368276 "[TargetLowering] SimplifyDemandedBits - call
SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT"
This introduced a false positive MemorySanitizer warning about use of
uninitialized memory in a vectorized crc function in Chromium. That
suggests maybe something is not right with this transformation. See
https://crbug.com/992853#c7 for a reproducer.
This also reverts the follow-up commits r368307 and r368308 which
depended on this.
> This patch attempts to peek through vectors based on the demanded
bits/elt of a particular ISD::EXTRACT_VECTOR_ELT node, allowing us to
avoid dependencies on ops that have no impact on the extract.
>
> In particular this helps remove some unnecessary
scalar->vector->scalar patterns.
>
> The wasm shift patterns are annoying - @tlively has indicated that the
wasm vector shift codegen are to be refactored in the near-term and
isn't considered a major issue.
>
> Differential Revision: https://reviews.llvm.org/D65887
llvm-svn: 368660
The file was modifiedllvm/test/CodeGen/X86/promote-vec3.ll
The file was modifiedllvm/test/CodeGen/X86/vec_smulo.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-mul.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-extended-extract.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
The file was modifiedllvm/test/CodeGen/X86/xor.ll
The file was modifiedllvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
The file was modifiedllvm/test/CodeGen/X86/shrink_vmul.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_umulo.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-arith.ll
Commit dc06b0bc9ad055d06535462d91bfc2a744b2f589 by maskray
[ELF] Don't special case symbolic relocations with 0 addend to ifunc in
writable locations
Currently the following 3 relocation types do not trigger the creation
of a canonical PLT (which changes STT_GNU_IFUNC to STT_FUNC and
redirects all references):
1) GOT-generating (`needsGot`) 2) PLT-generating (`needsPlt`) 3) R_ABS
with 0 addend in a writable location. This is used for
for ifunc function pointers in writable sections such as .data and
.toc.
This patch deletes case 3) to simplify the R_*_IRELATIVE generating
logic added in D57371. Other advantages:
* It is guaranteed no more than 1 R_*_IRELATIVE is created for an ifunc.
* PPC64: no need to special case ifunc in toc-indirect to toc-relative
relaxation. See D65755
The deleted elf::addIRelativeRelocs demonstrates that one-pass scan
through relocations makes several optimizations difficult. This is
something we can think about in the future.
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D65995
llvm-svn: 368661
The file was modifiedlld/ELF/Writer.cpp
The file was modifiedlld/ELF/Arch/PPC64.cpp
The file was modifiedlld/ELF/Relocations.cpp
The file was addedlld/test/ELF/aarch64-gnu-ifunc-nonpreemptable2.s
The file was modifiedlld/test/ELF/ppc64-toc-relax-ifunc.s
The file was modifiedlld/test/ELF/gnu-ifunc-canon.s