FailedChanges

Summary

  1. [ARM] Allocatable Global Register Variables for ARM (details)
  2. [AST] Attach comment in `/** doc */ typedef struct A {} B` to B as well (details)
  3. [lldb] [test] Enable lldb-server tests on NetBSD, and set XFAILs (details)
  4. [lldb] [Process/NetBSD] Implement thread name getting (details)
  5. [ARM,MVE] Add intrinsics for vector comparisons. (details)
  6. [ARM,MVE] Add InstCombine rules for pred_i2v / pred_v2i. (details)
  7. [NFC][Test] Add the vavg test for PowerPC (details)
  8. [RISCV] Set triple based on -march flag (details)
  9. [RISCV] Add assembly mnemonic spell checking (details)
  10. Fix signed/unsigned comparison warning. NFCI. (details)
  11. [X86][SSE] Add test for extractelement with multiple uses (details)
  12. Fix "not all control paths return a value" warning. NFCI. (details)
Commit 2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77 by anna.welker
[ARM] Allocatable Global Register Variables for ARM
      Provides support for using r6-r11 as globally scoped
     register variables. This requires a -ffixed-rN flag
     in order to reserve rN against general allocation.
      If for a given GRV declaration the corresponding flag
     is not found, or the the register in question is the
     target's FP, we fail with a diagnostic.
      Differential Revision: https://reviews.llvm.org/D68862
The file was modifiedclang/lib/Basic/Targets/ARM.h
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedclang/include/clang/Basic/DiagnosticGroups.td
The file was addedllvm/test/CodeGen/ARM/reg-alloc-fixed-r6-vla.ll
The file was modifiedclang/lib/Driver/ToolChains/Arch/ARM.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was addedllvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll
The file was addedclang/test/Sema/arm-global-regs.c
The file was modifiedllvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
The file was modifiedclang/lib/Basic/Targets/ARM.cpp
The file was modifiedclang/docs/ClangCommandLineReference.rst
The file was addedllvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
The file was addedllvm/test/CodeGen/Thumb/callee_save_reserved.ll
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was addedclang/test/Driver/arm-reserved-reg-options.c
The file was addedllvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll
The file was modifiedllvm/lib/Target/ARM/ARMFrameLowering.cpp
The file was modifiedclang/include/clang/Basic/TargetInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.cpp
The file was addedllvm/test/Feature/reserve_global_reg.ll
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedllvm/lib/Target/ARM/ARM.td
Commit a433e7141fb3f697e6430437ee73b19076603c1b by sam.mccall
[AST] Attach comment in `/** doc */ typedef struct A {} B` to B as well
as A.
Summary: Semantically they're the same thing, and it's important when
the underlying struct is anonymous.
There doesn't seem to be a problem attaching the same comment to
multiple things as it already happens with `/** doc */ int a, b;`
This affects an Index test but the results look better (name present,
USR points to the typedef).
Fixes https://github.com/clangd/clangd/issues/189
Reviewers: kadircet, lh123
Subscribers: ilya-biryukov, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D70203
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/test/Sema/warn-documentation.cpp
The file was modifiedclang-tools-extra/clangd/unittests/XRefsTests.cpp
The file was modifiedclang/test/Index/annotate-comments-typedef.m
Commit e8924d6403eba06438f669e434eee11016f20a67 by mgorny
[lldb] [test] Enable lldb-server tests on NetBSD, and set XFAILs
Differential Revision: https://reviews.llvm.org/D70335
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteThreadsInStopReply.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/register-reading/TestGdbRemoteGPacket.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemote_qThreadStopInfo.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteKill.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/signal-filtering/TestGdbRemote_QPassSignals.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteAttach.py
The file was modifiedlldb/packages/Python/lldbsuite/test/dotest.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteProcessInfo.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries-svr4/TestGdbRemoteLibrariesSvr4Support.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteAuxvSupport.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/thread-name/TestGdbRemoteThreadName.py
Commit 23a766dcad47993f632ab22ab3a8f3dc977bd838 by mgorny
[lldb] [Process/NetBSD] Implement thread name getting
Implement thread name getting sysctl() on NetBSD.  Also fix the
incorrect type in pthread_setname_np() in the relevant test.
Differential Revision: https://reviews.llvm.org/D70363
The file was modifiedlldb/source/Plugins/Process/NetBSD/NativeThreadNetBSD.cpp
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/thread-name/TestGdbRemoteThreadName.py
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/thread-name/main.cpp
Commit 4a4dd85e5ab51aa8c01c690cd14205af157178e7 by simon.tatham
[ARM,MVE] Add intrinsics for vector comparisons.
This adds the `vcmp` family of ACLE MVE intrinsics: vector/vector,
vector/scalar, and the predicated forms of both. All are represented
using standard existing IR: vector/scalar comparisons are represented by
making a vector out of the scalar first, and predicated forms are
represented by taking the bitwise AND of the input predicate and the
output of the comparison. Existing LLVM-side tests demonstrate that ISel
will pattern-match all of that back down to single MVE VCMPs.
The idiom of handling a vector/scalar operation by generating IR to
expand the scalar into a second vector is going to be needed for a lot
of MVE intrinsics, so to make that easy, I've provided a helper function
that automatically works out the element count.
The comparison intrinsics are the first ones that have to //return// a
predicate, in the user-facing `mve_pred16_t` format. This means we have
to use the `arm_mve_pred_v2i` low-level intrinsic to convert it back
from the logical `<n x i1>` form used in IR. I've done that explicitly
in the code gen specification for the builtins, because it happens much
more rarely in the ACLE API than passing a Predicate as input, so it
didn't seem worth automating in MveEmitter.
Reviewers: ostannard, MarkMurrayARM, dmgreen
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D70297
The file was addedclang/test/CodeGen/arm-mve-intrinsics/compare.c
The file was modifiedclang/include/clang/Basic/arm_mve_defs.td
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/include/clang/Basic/arm_mve.td
Commit f4f77aa53e5b872bd8a93c3a193714d8eba9578c by simon.tatham
[ARM,MVE] Add InstCombine rules for pred_i2v / pred_v2i.
If you're writing C code using the ACLE MVE intrinsics that passes the
result of a vcmp as input to a predicated intrinsic, e.g.
  mve_pred16_t pred = vcmpeqq(v1, v2);
v_out = vaddq_m(v_inactive, v3, v4, pred);
then clang's codegen for the compare intrinsic will create calls to
`@llvm.arm.mve.pred.v2i` to convert the output of `icmp` into an
`mve_pred16_t` integer representation, and then the next intrinsic will
call `@llvm.arm.mve.pred.i2v` to convert it straight back again. This
will be visible in the generated code as a `vmrs`/`vmsr` pair that move
the predicate value pointlessly out of `p0` and back into it again.
To prevent that, I've added InstCombine rules to remove round trips of
the form `v2i(i2v(x))` and `i2v(v2i(x))`. Also I've taught InstCombine
about the known and demanded bits of those intrinsics. As a result, you
now get just the generated code you wanted:
  vpt.u16 eq, q1, q2
vaddt.u16 q0, q3, q4
Reviewers: ostannard, MarkMurrayARM, dmgreen
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70313
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was addedllvm/test/CodeGen/Thumb2/mve-vpt-from-intrinsics.ll
The file was addedllvm/test/Transforms/InstCombine/ARM/mve-v2i2v.ll
Commit 03e7fb2e075e2cfca7a0c9e3730a48d52101dec2 by qshanz
[NFC][Test] Add the vavg test for PowerPC
The file was addedllvm/test/CodeGen/PowerPC/vavg.ll
Commit c00e5cf29d49e51701b00382a3f41a4dfe1c0c0f by simon.cook
[RISCV] Set triple based on -march flag
For RISC-V the value provided to -march should determine whether to
compile for 32- or 64-bit RISC-V irrespective of the target provided to
the Clang driver. This adds a test for this flag for RISC-V and sets the
Target architecture correctly in these cases.
Differential Revision: https://reviews.llvm.org/D54214
The file was modifiedclang/test/Driver/riscv-arch.c
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/lib/Driver/Driver.cpp
Commit eedb9648229ff14bf8d5a526099f765ea23f3777 by simon.cook
[RISCV] Add assembly mnemonic spell checking
Summary: This allows the assembler to suggest alternative assembly
mnemonics when an invalid one has been provided.
Reviewers: asb, lenary, lewis-revill
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, apazos, sabuasal, niosHD,
kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01,
MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna,
Jim, s.egerton, pzheng, sameer.abuasal, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69894
The file was addedllvm/test/MC/RISCV/invalid-instruction-spellcheck.s
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit 9df9dec926e2782e4f62b5a39f18619c7d928eba by llvm-dev
Fix signed/unsigned comparison warning. NFCI.
The file was modifiedllvm/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp
Commit b68191e729e0059c4edf7a3dbfde2bf38f419240 by llvm-dev
[X86][SSE] Add test for extractelement with multiple uses
Mentioned in D70267
The file was modifiedllvm/test/CodeGen/X86/extractelement-load.ll
Commit 1e3cc06d986dd04b0973ade251e9f2e129315509 by llvm-dev
Fix "not all control paths return a value" warning. NFCI.
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp