FailedChanges

Summary

  1. [MLIR][mlir-spirv-cpu-runner] A pass to emulate a call to kernel in LLVM (details)
  2. [clang-fuzzer] CreateAndRunJITFunc - fix use after move static analyzer warning. (details)
  3. [llvm-ar][Object] Fix detection of need for 64-bit archive symbol tables (details)
  4. [DAGCombine] Add test case showing incorrect DAGCombine optimization (details)
  5. [MLIR][mlir-spirv-cpu-runner] A SPIR-V cpu runner prototype (details)
  6. [clangd] Fix remote index build failures due to lack of proto dependency (details)
  7. [LV] Add cost-model test for AArch64 select costs. (details)
  8. [AMDGPU] Make more use of printNamedBit in AMDGPUInstPrinter. NFC. (details)
  9. [InstCombine] Add bswap test pattern using bitreverse intrinsic (details)
  10. [lldb][NFC] Make GetShellSafeArgument simpler and faster (details)
  11. [clangd] NFC: Update FIXME comment regarding lack of c/dtor support (details)
  12. [InstCombine] collectBitParts - add bitreverse intrinsic support. (details)
  13. Fix SBError::SetErrorToGenericError (details)
  14. [TableGen] [tests] Change integer ranges to use new '...' punctuation (details)
  15. [analyzer] [NFC] Simplify SVal::getAsLocSymbol function using existing functions (details)
  16. [VE] Support atomic store (details)
  17. [VE] Add vector logical instructions (details)
  18. [VE] Add vector shift instructions (details)
  19. [X86] Use mtriple instead of march in MIR tests (details)
  20. [AArch64] Add 2 cases where insertelement lowering could be improved. (details)
  21. [OpenMP] changing OMP rtl to use shared memory instead of env variable (details)
  22. [InstCombine] Add bswap test pattern using truncates (details)
  23. [libc++] Add a CI jobs to test the Standalone builds (details)
  24. [SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination (details)
  25. Revert "[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination" (details)
  26. [SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination (details)
  27. Unconfuse gcc5.3 after 2e204e23911b1f / D87528 (details)
  28. [libc++] Fix indentation of buildkite-pipeline.yml (details)
  29. [lld][ELF] Don't write output to the test directory. NFC. (details)
  30. [clang][unittest] Don't hardcode the string "Assertion" (details)
  31. [AMDGPU] Avoid unused variable warning in Release builds. NFC. (details)
  32. Fix issue in cortex-a57 sched model (details)
  33. [mlir][Linalg] Add basic support for TileAndFuse on Linalg on tensors. (details)
  34. [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate (details)
  35. [lldb][PDB] Add ObjectFile PDB plugin (details)
  36. [DebugInfo][dexter] Add dexter tests for escaped locals (details)
  37. [SVE][AArch64] Fix TypeSize warning in loop vectorization legality (details)
  38. [SVE][AArch64] Fix TypeSize warning in GEP cost analysis (details)
  39. [SVE][InstCombine] Fix TypeSize warning in canReplaceGEPIdxWithZero (details)
  40. [SVE] Fix TypeSize warning in llvm::getGEPInductionOperand (details)
  41. [mlir][vector] Update doc strings for insert_map/extract_map and fix insert_map semantic (details)
Commit cae4067ec1cdf7846aa46dab13d3bc1f58b76016 by antiagainst
[MLIR][mlir-spirv-cpu-runner] A pass to emulate a call to kernel in LLVM

This patch introduces a pass for running
`mlir-spirv-cpu-runner` - LowerHostCodeToLLVMPass.

This pass emulates `gpu.launch_func` call in LLVM dialect and lowers
the host module code to LLVM. It removes the `gpu.module`, creates a
sequence of global variables that are later linked to the varables
in the kernel module, as well as a series of copies to/from
them to emulate the memory transfer to/from the host or to/from the
device sides. It also converts the remaining Standard dialect into
LLVM dialect, emitting C wrappers.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D86112
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was modifiedmlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h
The file was addedmlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
The file was addedmlir/test/Conversion/SPIRVToLLVM/lower-host-to-llvm-calls.mlir
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt
Commit e4991867fb5ace434640bfacfd28720ad031d33c by llvm-dev
[clang-fuzzer] CreateAndRunJITFunc - fix use after move static analyzer warning.

We were using the unique_ptr M to determine the triple after it had been moved in the EngineBuilder constructor.
The file was modifiedclang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp
Commit 2add7c5cf3ebbba629d2756b3e91728e55b40881 by andrew.ng
[llvm-ar][Object] Fix detection of need for 64-bit archive symbol tables

The code to detect the requirement for 64-bit offsets in the archive
symbol table was not correctly accounting for the archive file signature
and the size of all the contents of the symbol table itself, e.g. the
symbol table's header and string table. Also was not considering the
variation in symbol table formats. This could result in the creation of
large archives with a corrupt symbol table.

Change the testing environment variable SYM64_THRESHOLD to be an
absolute value rather than a power of 2 in order to enable precise
testing of this detection code.

Differential Revision: https://reviews.llvm.org/D89891
The file was modifiedllvm/test/Object/archive-symtab.test
The file was modifiedllvm/lib/Object/ArchiveWriter.cpp
Commit ffa6d2afa4a6f35e2e99172a17d489bcec7f0353 by fraser
[DAGCombine] Add test case showing incorrect DAGCombine optimization

This optmization produces incorrect results when the vector element type
is not byte-sized. Related to D78568.
The file was addedllvm/test/CodeGen/AMDGPU/extract-load-i1.ll
Commit 89808ce7343b22586bfd0d3fafddcdbba94fbcbb by antiagainst
[MLIR][mlir-spirv-cpu-runner] A SPIR-V cpu runner prototype

This patch introduces a SPIR-V runner. The aim is to run a gpu
kernel on a CPU via GPU -> SPIRV -> LLVM conversions. This is a first
prototype, so more features will be added in due time.

- Overview
The runner follows similar flow as the other runners in-tree. However,
having converted the kernel to SPIR-V, we encode the bind attributes of
global variables that represent kernel arguments. Then SPIR-V module is
converted to LLVM. On the host side, we emulate passing the data to device
by creating in main module globals with the same symbolic name as in kernel
module. These global variables are later linked with ones from the nested
module. We copy data from kernel arguments to globals, call the kernel
function from nested module and then copy the data back.

- Current state
At the moment, the runner is capable of running 2 modules, nested one in
another. The kernel module must contain exactly one kernel function. Also,
the runner supports rank 1 integer memref types as arguments (to be scaled).

- Enhancement of JitRunner and ExecutionEngine
To translate nested modules to LLVM IR, JitRunner and ExecutionEngine were
altered to take an optional (default to `nullptr`) function reference that
is a custom LLVM IR module builder. This allows to customize LLVM IR module
creation from MLIR modules.

Reviewed By: ftynse, mravishankar

Differential Revision: https://reviews.llvm.org/D86108
The file was addedmlir/test/mlir-spirv-cpu-runner/simple_add.mlir
The file was modifiedmlir/lib/ExecutionEngine/ExecutionEngine.cpp
The file was addedmlir/test/mlir-spirv-cpu-runner/CMakeLists.txt
The file was modifiedmlir/tools/CMakeLists.txt
The file was addedmlir/test/mlir-spirv-cpu-runner/double.mlir
The file was modifiedmlir/include/mlir/ExecutionEngine/JitRunner.h
The file was modifiedmlir/examples/toy/Ch7/toyc.cpp
The file was addedmlir/test/mlir-spirv-cpu-runner/lit.local.cfg
The file was addedmlir/test/mlir-spirv-cpu-runner/mlir_test_spirv_cpu_runner_c_wrappers.cpp
The file was modifiedmlir/test/lit.cfg.py
The file was modifiedmlir/examples/toy/Ch6/toyc.cpp
The file was modifiedmlir/include/mlir/ExecutionEngine/ExecutionEngine.h
The file was addedmlir/tools/mlir-spirv-cpu-runner/CMakeLists.txt
The file was addedmlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
The file was modifiedmlir/test/CMakeLists.txt
The file was modifiedmlir/test/lit.site.cfg.py.in
The file was modifiedmlir/lib/ExecutionEngine/JitRunner.cpp
The file was modifiedmlir/CMakeLists.txt
Commit 58d0ef2d0466a893ab400f6a9829057b9d851038 by kbobyrev
[clangd] Fix remote index build failures due to lack of proto dependency

Previous attempt (15f6bad6d74a993e366c8fc93a9c91f213ac6bc3) introduced
add_dependencies but unfortunately it does not actually add a dependency
between RemoteIndexProto and RemoteIndexServiceProto. This is likely due
to some requirements of it that clang_add_library violates.

As a workaround, we will link RemoteIndexProto library to
RemoteIndexServiceProto which is logical because the library can not be
without linking to RemoteIndexProto anyway.
The file was modifiedclang-tools-extra/clangd/index/remote/CMakeLists.txt
Commit 1747aae9fc64448fb9b4f715dcd327c94f2fa4a6 by flo
[LV] Add cost-model test for AArch64 select costs.

Currently, the cost of some compare/select patterns is overestimated on
AArch64.
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
Commit 0ca4124798df6518bb7b3b3722e0ab788acdd494 by jay.foad
[AMDGPU] Make more use of printNamedBit in AMDGPUInstPrinter. NFC.
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
Commit 16f126df437f9ea19383c5486181c5e2797227f2 by llvm-dev
[InstCombine] Add bswap test pattern using bitreverse intrinsic

This is mainly to help with future better bitreverse folding support but we can test it via bswap matching for now.
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit d0ee1d8efe804b3184b1073cd367a307867f1372 by Raphael Isemann
[lldb][NFC] Make GetShellSafeArgument simpler and faster

Escaping by inserting characters in the middle of a std::string isn't cheap.
It's much more verbose than just prepending a backslash in a loop.
The file was modifiedlldb/source/Utility/Args.cpp
Commit 1704704e762f232e827849ee881ebe74b5db7ef1 by kbobyrev
[clangd] NFC: Update FIXME comment regarding lack of c/dtor support

Both `SymbolKind` and `indexSymbolKindToSymbolKind` support constructors and
separate them into a different category from regular methods.

Reviewed By: kadircet

Differential Revision: https://reviews.llvm.org/D89935
The file was modifiedclang-tools-extra/clangd/FindSymbols.cpp
The file was modifiedclang-tools-extra/clangd/XRefs.cpp
Commit 532f3bec3e019a3e6089edf6bd21e9b9b540542b by llvm-dev
[InstCombine] collectBitParts - add bitreverse intrinsic support.
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 206e8d8905035f6e9049b97c9cd8af0eaa5aa118 by Raphael Isemann
Fix SBError::SetErrorToGenericError

`SBError::SetErrorToGenericError` should call `Status::SetErrorToGenericError`,
not `Status::SetErrorToErrno`.

Reviewed By: teemperor

Differential Revision: https://reviews.llvm.org/D90151
The file was addedlldb/test/API/python_api/sberror/TestSBError.py
The file was modifiedlldb/source/API/SBError.cpp
Commit 26e2e9f2de7efdfb843a5440e7a94c4e919efd7a by paul
[TableGen] [tests] Change integer ranges to use new '...' punctuation

Differential Revision: https://reviews.llvm.org/D90057
The file was modifiedllvm/test/TableGen/FixedLenDecoderEmitter/conflict.td
The file was modifiedllvm/test/TableGen/Common/reg-with-subregs-common.td
The file was modifiedllvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td
The file was modifiedllvm/unittests/TableGen/Automata.td
Commit 32efb81ea60a9e99571923bf9308598f6cd341f2 by dpetrov
[analyzer] [NFC] Simplify SVal::getAsLocSymbol function using existing functions

Summary: Method of obtaining MemRegion from LocAsInteger/MemRegionVal already exists in SVal::getAsRegion function. Replace repetitive conditions in SVal::getAsLocSymbol with SVal::getAsRegion function.

Differential Revision: https://reviews.llvm.org/D89982
The file was modifiedclang/lib/StaticAnalyzer/Core/SVals.cpp
Commit cfefef50c18a481040203f15b55edf89c1fafceb by marukawa
[VE] Support atomic store

Support atomic store instructions and add a regression test.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90137
The file was addedllvm/test/CodeGen/VE/atomic_store.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
Commit 83cb423c6e19f3aad819b89140b1d74203b23180 by marukawa
[VE] Add vector logical instructions

Add VAND/VOR/VXOE/VEQV/VLDZ/VPCNT/VBRV/VSEQ instrucitons and regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90141
The file was addedllvm/test/MC/VE/VXOR.s
The file was addedllvm/test/MC/VE/VLDZ.s
The file was addedllvm/test/MC/VE/VEQV.s
The file was addedllvm/test/MC/VE/VOR.s
The file was addedllvm/test/MC/VE/VAND.s
The file was addedllvm/test/MC/VE/VSEQ.s
The file was addedllvm/test/MC/VE/VPCNT.s
The file was addedllvm/test/MC/VE/VBRV.s
The file was modifiedllvm/lib/Target/VE/VEInstrVec.td
Commit 9d0db405b57b892d5dad75549dea942c337e9f0d by marukawa
[VE] Add vector shift instructions

Add VSLL/VSLD/VSRL/VSLA/VSLAX/VSRA/VSRAX/VSFA instructionss.  Add
additonal AsmParser for VSLD special operand.  Also add regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90143
The file was addedllvm/test/MC/VE/VSLD.s
The file was addedllvm/test/MC/VE/VSLA.s
The file was addedllvm/test/MC/VE/VSRAX.s
The file was modifiedllvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
The file was addedllvm/test/MC/VE/VSLAX.s
The file was addedllvm/test/MC/VE/VSLL.s
The file was modifiedllvm/lib/Target/VE/VEInstrVec.td
The file was addedllvm/test/MC/VE/VSFA.s
The file was addedllvm/test/MC/VE/VSRA.s
Commit 2030db328ae319b53c358923009f3d48d6fd4b52 by llvm-dev
[X86] Use mtriple instead of march in MIR tests
The file was modifiedllvm/test/CodeGen/X86/opt_phis2.mir
The file was modifiedllvm/test/CodeGen/X86/x87-reg-usage.mir
The file was modifiedllvm/test/CodeGen/X86/unreachable-mbb-undef-phi.mir
The file was modifiedllvm/test/CodeGen/X86/opt_phis.mir
Commit a562dc82a8d9488d35ff535302716141bc6feaa3 by flo
[AArch64] Add 2 cases where insertelement lowering could be improved.
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
Commit d6a0957467e86d5a87964d45fae18733e212c86f by Andrey.Churbanov
[OpenMP] changing OMP rtl to use shared memory instead of env variable

Patch by Erdner, Todd <todd.erdner@intel.com>

Differential Revision: https://reviews.llvm.org/D89898
The file was modifiedopenmp/runtime/src/kmp_runtime.cpp
The file was modifiedopenmp/runtime/cmake/LibompHandleFlags.cmake
The file was modifiedopenmp/runtime/cmake/config-ix.cmake
Commit 0ef6a25e195bafa285d3b957f247bfb23b2cf704 by llvm-dev
[InstCombine] Add bswap test pattern using truncates
The file was modifiedllvm/test/Transforms/InstCombine/bswap.ll
Commit d3024a074be09f6589eccac00cecabccd8258f2d by Louis Dionne
[libc++] Add a CI jobs to test the Standalone builds
The file was modifiedlibcxx/src/CMakeLists.txt
The file was modifiedlibcxx/utils/ci/run-buildbot.sh
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
Commit 4604441386dc5fcd3165f4b39f5fa2e2c600f1bc by joe.ellis
[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination

The modified code in visitSTORE was missing a scalable vector check, and still
using the now deprecated implicit cast of TypeSize to uint64_t through the
overloaded operator. This patch fixes these issues.

This brings the logic in line with the comment on the context line immediately
above the added precondition.

Add a test in Redundantstores.ll that the warning is not triggered.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/AArch64/Redundantstore.ll
Commit 6536d6040f5cd20d554901e265519b80dd8119f2 by peter.waller
Revert "[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination"

This reverts commit 4604441386dc5fcd3165f4b39f5fa2e2c600f1bc.

Reverting because it was not the intended version of the patch, which
follows this patch.
The file was modifiedllvm/test/CodeGen/AArch64/Redundantstore.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 5b742a0c106fbed11779d6dd99854a6f97643524 by peter.waller
[SVE][CodeGen][DAGCombiner] Fix TypeSize warning in redundant store elimination

The modified code in visitSTORE was missing a scalable vector check, and still
using the now deprecated implicit cast of TypeSize to uint64_t through the
overloaded operator. This patch fixes these issues.

This brings the logic in line with the comment on the context line immediately
above the added precondition.

Add a test in sve-redundant-store.ll that the warning is not triggered.

Differential Revision: https://reviews.llvm.org/D89701
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-redundant-store.ll
Commit c686dfd61705f33419875b22eb08bd197a72cd18 by thakis
Unconfuse gcc5.3 after 2e204e23911b1f / D87528

The local variable CmpResult added in that change shadowed the
type CmpResult, which confused an older gcc. Rename the variable
CmpResult to APFloatCmpResult.
The file was modifiedclang/lib/AST/ExprConstant.cpp
Commit 88374f76ee19d21b2c64425c95f05a20d37a84fa by Louis Dionne
[libc++] Fix indentation of buildkite-pipeline.yml
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
Commit 85e2af7ffeed1e4d2e07b502a2030eff09a06636 by benny.kra
[lld][ELF] Don't write output to the test directory. NFC.
The file was modifiedlld/test/ELF/lto/warn-backrefs.ll
Commit dd7095f52bda36e0f3cd37574a1cb97c7a46cffe by benny.kra
[clang][unittest] Don't hardcode the string "Assertion"

This depends on the libc implementation. Use the string from the
assertion message instead. Overly specific, but so is this entire test.
The file was modifiedclang/unittests/Basic/LineOffsetMappingTest.cpp
Commit b777d3049652746881b74152416e3ffb025a887c by benny.kra
[AMDGPU] Avoid unused variable warning in Release builds. NFC.

SIRegisterInfo.cpp:480:19: error: unused variable 'SOffset'
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Commit a877bda397bb0ace3688c687281dbc3e8d00204a by eleviant
Fix issue in cortex-a57 sched model

Differential revision: https://reviews.llvm.org/D90152
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
Commit 37e0fdd072a95b51bcd0eb6b08d2762aa304e766 by nicolas.vasilache
[mlir][Linalg] Add basic support for TileAndFuse on Linalg on tensors.

This revision allows the fusion of the producer of input tensors in the consumer under a tiling transformation (which produces subtensors).
Many pieces are still missing (e.g. support init_tensors, better refactor LinalgStructuredOp interface support, try to merge implementations and reuse code) but this still allows getting started.

The greedy pass itself is just for testing purposes and will be extracted in a separate test pass.

Differential revision: https://reviews.llvm.org/D89491
The file was addedmlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h
Commit e74f66125ebb3b43720b6803b4715c8a9c361a2f by eleviant
[ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90150
The file was modifiedllvm/lib/Target/ARM/ARMScheduleA57.td
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
The file was modifiedllvm/lib/Target/ARM/ARMSchedule.td
Commit 242e1e9910441ad00118e580e4cbd5743c77ea5e by zequanwu
[lldb][PDB] Add ObjectFile PDB plugin

To allow loading PDB file with `target symbols add` command.

Differential Revision: https://reviews.llvm.org/D89812
The file was addedlldb/test/Shell/ObjectFile/PDB/object.test
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h
The file was addedlldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/CMakeLists.txt
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
The file was addedlldb/source/Plugins/ObjectFile/PDB/ObjectFilePDB.cpp
The file was modifiedlldb/source/Plugins/ObjectFile/CMakeLists.txt
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/PdbIndex.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/NativePDB/PdbIndex.h
The file was addedlldb/source/Plugins/ObjectFile/PDB/CMakeLists.txt
The file was addedlldb/source/Plugins/ObjectFile/PDB/ObjectFilePDB.h
Commit 66d03af88c2e4932ae53787e07f502b90ab220cc by orlando.hyams
[DebugInfo][dexter] Add dexter tests for escaped locals

Recently there has been renewed interest in improving debug-info for variables
that (partially or otherwise) live on the stack in optimised code.

At the moment instcombine speculates that stack slots are probably going to be
promoted to registers, and prepares the debug-info accordingly. It runs a
function called LowerDbgDeclare which converts dbg.declares to a set of
dbg.values after loads, and before stores and calls. Sometimes the stack
location remains (e.g. for escaped locals). If any dbg.values become undef
where the stack location is still valid we end up unnecessarily reducing
variable location coverage due to our inability to track multiple locations
simultaneously. There is a flag to disable this feature
(-instcombine-lower-dbg-declare=0), which prevents this conversion at the cost
of sometimes providing incorrect location info in the face of DSE, DCE, GVN,
CSE etc.

This has been discussed fairly extensively on PR34136.

The idea of these tests is to provide examples of situations that we should
consider when designing a new system, to aid discussions and eventually help
evaluate the implementation.

Dexter isn't ideal for observing specific optimisation behaviour. Writing an
exaustive test suite would be difficult, and the resultant suite would be
fragile. However, I think having some concrete executable examples is useful
at least as a reference.

Differential Revision: https://reviews.llvm.org/D89543
The file was addeddebuginfo-tests/dexter-tests/memvars/inlining.c
The file was addeddebuginfo-tests/dexter-tests/memvars/struct-dse.c
The file was addeddebuginfo-tests/dexter-tests/memvars/ctrl-flow.c
The file was addeddebuginfo-tests/dexter-tests/memvars/const-branch.c
The file was addeddebuginfo-tests/dexter-tests/memvars/ptr-to.c
The file was addeddebuginfo-tests/dexter-tests/memvars/inlining-dse.c
The file was addeddebuginfo-tests/dexter-tests/memvars/bitcast.c
The file was addeddebuginfo-tests/dexter-tests/memvars/implicit-ptr.c
The file was addeddebuginfo-tests/dexter-tests/memvars/loop.c
Commit 467e5cf40f5da942419624d6a722567976b28a45 by joe.ellis
[SVE][AArch64] Fix TypeSize warning in loop vectorization legality

The warning would fire when calling isDereferenceableAndAlignedInLoop
with a scalable load. Calling isDereferenceableAndAlignedInLoop with a
scalable load would result in the use of the now deprecated implicit
cast of TypeSize to uint64_t through the overloaded operator.

This patch fixes this issue by:

- no longer considering vector loads as candidates in
  canVectorizeWithIfConvert. This doesn't make sense in the context of
  identifying scalar loads to vectorize.

- making use of getFixedSize inside isDereferenceableAndAlignedInLoop --
  this removes the dependency on the deprecated interface, and will
  trigger an assertion error if the function is ever called with a
  scalable type.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D89798
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/sve-scalable-load-in-loop.ll
The file was modifiedllvm/lib/Analysis/Loads.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
Commit 0383a1a8c230581aec4f2d9d4bfb5f5ed32d2bf5 by joe.ellis
[SVE][AArch64] Fix TypeSize warning in GEP cost analysis

The warning would fire when calling getGEPCost for analyzing the cost of
a GEP instruction. This would result in the use of the now deprecated
implicit cast of TypeSize to uint64_t through the overloaded operator.

This patch fixes the issue by using getKnownMinSize instead of the
implicit cast. This is possible because the code is already
scalable-vector aware. The semantic behaviour of the code is unchanged
by this patch.

Reviewed By: sdesmalen, fpetrogalli

Differential Revision: https://reviews.llvm.org/D89872
The file was addedllvm/test/Analysis/CostModel/AArch64/cost-scalable-vector-gep.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
Commit 0f8350559325db35e0ee3423db5d29113e4eec12 by joe.ellis
[SVE][InstCombine] Fix TypeSize warning in canReplaceGEPIdxWithZero

The warning would fire when calling canReplaceGEPIdxWithZero on a GEP
whose source element type is a scalable vector. The size of scalable
vector types is not known, so this optimization cannot be performed.

This patch fixes the issue by:

- bailing out early in this routine if the GEP instruction's source
  element type is a scalable vector.

- making use of getFixedSize -- this removes the dependency on the
  deprecated interface.

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D89968
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
The file was addedllvm/test/Transforms/InstCombine/gep-can-replace-gep-idx-with-zero-typesize.ll
Commit bf60bb26ecbf4dace2a03886180be66b3ef5608a by joe.ellis
[SVE] Fix TypeSize warning in llvm::getGEPInductionOperand

We do not need to use the implicit cast here. We can instead can rely on
a comparison between two TypeSize objects instead. This algorithm will
work fine with scalable vectors.

Reviewed By: DavidTruby

Differential Revision: https://reviews.llvm.org/D90146
The file was addedllvm/test/Analysis/LoopAccessAnalysis/gep-induction-operand-typesize-warning.ll
The file was modifiedllvm/lib/Analysis/VectorUtils.cpp
Commit bd07be4f3f7fc062c7c80122b8796838be91abd3 by thomasraoux
[mlir][vector] Update doc strings for insert_map/extract_map and fix insert_map semantic

Based on discourse discussion, fix the doc string and remove examples with
wrong semantic. Also fix insert_map semantic by adding missing operand for
vector we are inserting into.

Differential Revision: https://reviews.llvm.org/D89563
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Dialect/Vector/vector-distribution.mlir
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp