SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower binary v4f64 (details)
  2. [AMDGPU] Regenerate shl shift tests (details)
  3. [MIPS] Regenerate shl/lshr shift tests (details)
  4. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  5. [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin (details)
  6. [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw (details)
  7. __patchable_function_entries: don't use linkage field 'unique' with (details)
  8. [AMDGPU] Add gfx8 assembler and disassembler test cases (details)
  9. [MC][ELF] Emit a relocation if target is defined in the same section and (details)
  10. Fix "pointer is null" static analyzer warning. NFCI. (details)
  11. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  12. [RISCV] Check register class for AMO memory operands (details)
Commit 66e39067edbfdb1469be001ebb053530a608b532 by llvm-dev
[X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower binary v4f64
shuffles.
Only perform this if we are shuffling lower and upper lane elements
across the lanes (otherwise splitting to lower xmm shuffles would be
better).
This is a regression if we shuffle build_vectors due to getVectorShuffle
canonicalizing 'blend of splat' build vectors, for now I've set this not
to shuffle build_vector nodes at all to avoid this.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/avx-unpack.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
The file was modifiedllvm/test/CodeGen/X86/subvector-broadcast.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
Commit 065eefcfe969249a7df9d1ef4a0e468606b25359 by llvm-dev
[AMDGPU] Regenerate shl shift tests
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
Commit a888277897f75b2952d96de229fff57519cfc363 by llvm-dev
[MIPS] Regenerate shl/lshr shift tests
The file was modifiedllvm/test/CodeGen/Mips/llvm-ir/lshr.ll
The file was modifiedllvm/test/CodeGen/Mips/llvm-ir/shl.ll
Commit ad201691d5cc0f15f6f885f3847dcc6440ee3de5 by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use cast<> instead of dyn_cast<> and move into its users where its
dereferenced immediately.
The file was modifiedclang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
Commit ebd26cc8c434f40fe8079ee823e7657b5138769f by maskray
[PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin
Darwin support has been removed.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D72063
The file was removedllvm/test/CodeGen/PowerPC/hello-reloc.s
The file was removedllvm/test/MC/MachO/PowerPC/lit.local.cfg
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
The file was removedllvm/test/MC/PowerPC/ppc-separator.s
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
The file was removedllvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
Commit de797ccdd74f46d5f637ccf66c78da9905a46f42 by alexandre.ganea
[NFC] Fix compilation of CrashRecoveryContext.cpp on mingw
Patch by Markus Böck.
Differential Revision: https://reviews.llvm.org/D72564
The file was modifiedllvm/lib/Support/CrashRecoveryContext.cpp
Commit 7fa5290d5bd5632d7a36a4ea9f46e81e04fb819e by maskray
__patchable_function_entries: don't use linkage field 'unique' with
-no-integrated-as
.section name, "flags"G, @type, GroupName[, linkage]
As of binutils 2.33, linkage cannot be 'unique'.  For integrated
assembler, we use both 'o' flag and 'unique' linkage to support
--gc-sections and COMDAT with lld.
https://sourceware.org/ml/binutils/2019-11/msg00266.html
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/AArch64/patchable-function-entry.ll
Commit 241f330d6bab52ab4e3a01cbb9a3edd417d07c59 by jay.foad
[AMDGPU] Add gfx8 assembler and disassembler test cases
Summary: This adds assembler tests for cases that were previously only
in the disassembler tests, and vice versa.
Reviewers: rampitec, arsenm, nhaehnle
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye,
jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72561
The file was modifiedllvm/test/MC/AMDGPU/gfx8_asm_all.s
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
Commit 2bfee35cb860859b436de0b780fbd00d68e198a4 by maskray
[MC][ELF] Emit a relocation if target is defined in the same section and
is non-local
For a target symbol defined in the same section, currently we don't emit
a relocation if VariantKind is VK_None (with few exceptions like RISC-V
relaxation), while GNU as emits one. This causes program behavior
differences with and without -ffunction-sections, and can break intended
symbol interposition in a -shared link.
```
.globl foo foo:
call foo      # no relocation. On other targets, may be written as b
foo, etc
call bar      # a relocation if bar is in another section (e.g.
-ffunction-sections)
call foo@plt  # a relocation
```
Unify these cases by always emitting a relocation. If we ever want to
optimize `call foo` in -shared links, we should emit a STB_LOCAL alias
and call via the alias.
ARM/thumb2-beq-fixup.s: we now emit a relocation to global_thumb_fn as
GNU as does. X86/Inputs/align-branch-64-2.s: we now emit R_X86_64_PLT32
to foo as GNU does.
ELF/relax.s: rewrite the test as target-in-same-section.s . We omitted
relocations to `global` and now emit R_X86_64_PLT32. Note, GNU as does
not emit a relocation for `jmp global` (maybe its own bug). Our new
behavior is compatible except `jmp global`.
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D72197
The file was modifiedllvm/lib/MC/ELFObjectWriter.cpp
The file was modifiedllvm/test/MC/X86/align-branch-64-2b.s
The file was modifiedllvm/test/MC/ARM/thumb2-beq-fixup.s
The file was modifiedlld/test/ELF/global-offset-table-position-aarch64.s
The file was modifiedllvm/test/MC/X86/align-branch-64-2c.s
The file was addedllvm/test/MC/ELF/target-in-same-section.s
The file was removedllvm/test/MC/ELF/relax.s
The file was modifiedllvm/test/MC/X86/align-branch-64-2a.s
The file was modifiedllvm/test/MC/ARM/thumb1-branch-reloc.s
Commit ada22c804cd956f3ee7cc9dc82e6d54ead8a4ffe by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
The file was modifiedclang/include/clang/Basic/SourceManager.h
Commit 54b2914accb4f5c9b58305fd6da405d20a47c452 by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use castAs<> instead of getAs<> since the pointers are dereferenced
immediately and castAs will perform the null assertion for us.
The file was modifiedclang/lib/AST/VTableBuilder.cpp
Commit 0113cf193f0610bb1a5dfa0bcd29c41a8965938a by jrtc27
[RISCV] Check register class for AMO memory operands
Summary: AMO memory operands use a custom parser in order to accept both
(reg) and 0(reg). However, the validation predicate used for these
operands was only checking that they were registers, and not the
register class, so non-GPRs (such as FPRs) were also accepted. Thus, fix
this by making the predicate check that they are GPRs.
Reviewers: asb, lenary
Reviewed By: asb, lenary
Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD,
kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01,
MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna,
Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72471
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoA.td
The file was modifiedllvm/test/MC/RISCV/rva-aliases-invalid.s
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp