Started 3 mo 14 days ago
Took 6 hr 4 min

Failed Build #974 (Feb 21, 2020 9:28:22 AM)

Changes
  1. AMDGPU/GlobalISel: Fix constant bus violation with source modifiers (details)
  2. AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy (details)
  3. AMDGPU/GlobalISel: Legalize G_FPOW (details)
  4. AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC (details)
  5. [ARM] Correct Formatting. NFC (details)
  6. AMDGPU/GlobalISel: Precommit xnor matching test (details)
  7. [ELF] Ignore the maximum of input section alignments for two cases (details)
  8. [ELF] Warn changed output section address (details)
  9. [lldb-vscode] Use libOption with tablegen to parse command line options. (details)
  10. [ELF] Shuffle .init_array/.fini_array with --shuffle-sections= (details)
  11. [TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls. (details)
  12. AMDGPU/GlobalISel: Fix xnor matching (details)
  13. AMDGPU/GlobalISel: Commit test changes I forgot to squash (details)
  14. GlobalISel: Fix narrowing of (G_ASHR i64:x, 32) (details)
  15. [AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll (details)
  16. [DSE,MSSA] Add debug counter. (details)
  17. [AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls. (details)
  18. [VectorCombine] refactor matching code to reduce duplication; NFC (details)
  19. [AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations (details)
  20. AMDGPU: Use default operand for VOP3P clamp (details)
  21. [SystemZ]  Return scalarized costs for vector instructions on older archs. (details)
  22. [gn build] Port 23444edf30b (details)
  23. [SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls (details)
  24. [X86] Fix SDLoc initialization (details)
  25. [VectorUtils] Move ToVectorTy to VectorUtils.h (NFC). (details)
  26. [DSE,MSSA] Dbg counters required assertions. Mark test accordingly. (details)
  27. [InstCombine] Use replaceOperand() in more places (details)
  28. [Clang interpreter] Rename Block.{h,cpp} to InterpBlock.{h,cpp} (details)
  29. [BFI] Fix missed BFI updates in MachineSink. (details)
  30. [InstCombine] Improve simplify demanded bits worklist management (details)
  31. [llvm][CodeGen] DAG Combiner folds for vscale. (details)
  32. [MLIR] Allow Loop dialect IfOp and ForOp to define values (details)
  33. [XCOFF][AIX] Put undefined symbol name into StringTable when neccessary (details)
  34. [LoopVectorize][X86] Regenerate tests. NFCI. (details)
  35. Fix MSVC "not all control paths return a value" warning. NFCI. (details)
  36. AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR (details)
  37. AMDGPU/GlobalISel: Select VOP3P instructions (details)
  38. AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2 (details)
  39. AMDGPU: Move dot intrinsic patterns to instruction def (details)
  40. [lldb/cmake] Enable more verbose find_package output. (details)
  41. AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max (details)
  42. [ARM] Change ARMAttributeParser::Parse to use support::endianness and simplify (details)
  43. [libc++] Do not set the `availability=XXX` feature when not testing against a system libc++ (details)
  44. [AArch64][SVE] Add backend support for splats of immediates (details)
  45. [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V (details)
  46. [mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V. (details)
  47. [MLIR] Remove constexpr from LoopOps.td (details)
  48. [Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q if possible (details)
  49. Move StandardOps/Ops.h to StandardOps/IR/Ops.h (details)
  50. [llvm][aarch64] SVE addressing modes. (details)
  51. [VectorCombine] refactor cost calcs to reduce duplication; NFC (details)
  52. [llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE. (details)
  53. [IR] Update BasicBlock::validateInstrOrdering comments, NFC (details)
  54. [X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix. (details)
  55. [macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat (details)
  56. Allow customized relative PYTHONHOME (details)
  57. [gn build] Port 1874dee5662 (details)
  58. [VectorCombine] refactor to reduce duplicated code; NFC (details)
  59. AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16 (details)

Started by upstream project LLDB Incremental build number 9816
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Started by upstream project LLDB Incremental build number 9817
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Started by upstream project LLDB Incremental build number 9818
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Started by upstream project LLDB Incremental build number 9820
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Started by upstream project LLDB Incremental build number 9821
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Started by upstream project LLDB Incremental build number 9822
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Started by upstream project LLDB Incremental build number 9823
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Started by upstream project LLDB Incremental build number 9824
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Started by upstream project LLDB Incremental build number 9825
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Started by upstream project LLDB Incremental build number 9826
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Started by upstream project LLDB Incremental build number 9827
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Started by upstream project LLDB Incremental build number 9828
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Started by upstream project LLDB Incremental build number 9829
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Started by upstream project LLDB Incremental build number 9830
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Started by upstream project LLDB Incremental build number 9831
originally caused by:

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This run spent:

  • 6 hr 51 min waiting;
  • 6 hr 4 min build duration;
  • 9 hr 2 min total from scheduled to completion.
Revision: 3a4296e9c1cdb53e0bf939b244790d257a6d5f26
  • refs/remotes/origin/master
Revision: b72f1448ce42f4e38f0c2a33418089f2320ab8f3
  • refs/remotes/origin/master
Revision: 3a4296e9c1cdb53e0bf939b244790d257a6d5f26
  • refs/remotes/origin/master
Test Result (1 failure / ±0)

Identified problems

Ninja target failed

Below is a link to the first failed ninja target.
Indication 1

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 2