Commit
b64aa8c715112ac4b9fd1ae8eb5ecb981ecd091a
by arsenm2AMDGPU/GlobalISel: Fix constant bus violation with source modifiers
This looked through copies to find the source modifiers, which may have been SGPR->VGPR copies added to avoid potential constant bus violations. Re-insert a copy to a VGPR if this happens.
|
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll |
Commit
fab4cdea3911b19d1b1819102aee0252cbd4eba4
by arsenm2AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy
|
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td |
Commit
79ff188addeeea127c7a7edd808c5821917d4bb6
by arsenm2AMDGPU/GlobalISel: Legalize G_FPOW
There are few differences from the DAG handling. First, the DAG handling uses a primitive selection pattern instead of custom legalizing it. Because of this, this makes use of source modifiers while the DAG does not.
Also instead of promoting f16, try to use the f16 log/exp. There's no f16 fmul_legacy, so widen just for the multiply, although I'm not sure that's the best solution.
|
 | llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll |
 | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir |
Commit
ac7abe0ba9ae4c6a2248cc3ef4e4fe7e6d270105
by arsenm2AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC
We have patterns for s_pack* selection, but they assume the inputs are a build_vector with 16-bit inputs, not a truncating build vector. Since there's still outstanding work for how to handle mismatched result and source element vector operations, and since I'm trying a different packed vector strategy than SelectionDAG, just manually select this for now.
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 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir |
Commit
83012cb217189bb6faa1256cc44fd0c306363264
by david.green[ARM] Correct Formatting. NFC
Also removed an unnecessary TODO that I don't believe is relevant for the instruction in question.
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 | llvm/lib/Target/ARM/ARMISelLowering.cpp |
Commit
89dc8fe6222041319e073ceb8ee0cb38d045ea16
by arsenm2AMDGPU/GlobalISel: Precommit xnor matching test
|
 | llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll |
Commit
6ed8e2014330b6a48d238cdc4357e788cdd6d445
by maskray[ELF] Ignore the maximum of input section alignments for two cases
Follow-up for D74286.
Notations:
* alignExpr: the computed ALIGN value * max_input_align: the maximum of input section alignments
This patch changes the following two cases to match GNU ld:
* When ALIGN is present, GNU ld sets output sh_addr to alignExpr, while lld use max(alignExpr, max_input_align) * When addrExpr is specified but alignExpr is not, GNU ld sets output sh_addr to addrExpr, while lld uses `advance(0, max_input_align)`
Note, sh_addralign is still set to max(alignExpr, max_input_align).
lma-align.test is enhanced a bit to check we don't overalign sh_addr.
fixSectionAlignments() sets addrExpr but not alignExpr for the `!hasSectionsCommand` case. This patch sets alignExpr as well so that max_input_align will be respected.
Reviewed By: grimar
Differential Revision: https://reviews.llvm.org/D74736
|
 | lld/ELF/Writer.cpp |
 | lld/test/ELF/linkerscript/lma-align.test |
 | lld/test/ELF/linkerscript/outsections-addr.s |
 | lld/test/ELF/linkerscript/section-align2.test |
 | lld/ELF/LinkerScript.cpp |
Commit
de0dda54d38137d0714c279a540074fe73822b8b
by maskray[ELF] Warn changed output section address
When the output section address (addrExpr) is specified, GNU ld warns if sh_addr is different. This patch implements the warning.
Note, LinkerScript::assignAddresses can be called more than once. We need to record the changed section addresses, and only report the warnings after the addresses are finalized.
Reviewed By: grimar
Differential Revision: https://reviews.llvm.org/D74741
|
 | lld/test/ELF/linkerscript/lma-align.test |
 | lld/test/ELF/linkerscript/section-align2.test |
 | lld/ELF/LinkerScript.cpp |
 | lld/ELF/LinkerScript.h |
 | lld/ELF/Writer.cpp |
Commit
c47e0e2d37d32ec56c760f1a2c9740d69c370b57
by Jonas Devlieghere[lldb-vscode] Use libOption with tablegen to parse command line options.
This change will bring lldb-vscode in line with how several other llvm tools process command line arguments and make it easier to add future options.
Differential revision: https://reviews.llvm.org/D74798
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 | lldb/tools/lldb-vscode/lldb-vscode.cpp |
 | lldb/tools/lldb-vscode/Options.td |
 | lldb/test/Shell/helper/toolchain.py |
 | lldb/tools/lldb-vscode/CMakeLists.txt |
 | lldb/test/Shell/VSCode/TestOptions.test |
Commit
dbd7281aa775a0e23c43a02583593900cd4c05be
by maskray[ELF] Shuffle .init_array/.fini_array with --shuffle-sections=
Useful for detecting static initialization order fiasco.
Reviewed By: grimar
Differential Revision: https://reviews.llvm.org/D74887
|
 | lld/ELF/Writer.cpp |
 | lld/test/ELF/shuffle-sections-init-fini.s |
Commit
42ec6fdce92090c02a10506fbdb2257fdbc2d1fd
by llvm-dev[TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls.
Minor refactor/cleanup before we begin adding non-uniform support.
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 | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
Commit
043ed2e22ac442c2116f5df6367d3889ea0b9de1
by arsenm2AMDGPU/GlobalISel: Fix xnor matching
We should try the generated matchers before the manual selection. This means the patterns are now handling the common cases, but the manual selection code is not yet dead. It's still handling the non-s32/s64 cases (like v2s16 and v2s32). Currently tablegen doesn't have a nice way to have a single pattern that covers multiple types.
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir |
Commit
6a479220b5e8b25ec3ffe193c463cb3fdaac0e06
by arsenm2AMDGPU/GlobalISel: Commit test changes I forgot to squash
These should have been in ac7abe0ba9ae4c6a2248cc3ef4e4fe7e6d270105
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir |
Commit
cab39e4b8c826ec5dfebe17a18137272022e64ac
by jay.foadGlobalISel: Fix narrowing of (G_ASHR i64:x, 32)
Reviewers: arsenm
Subscribers: jvesely, wdng, nhaehnle, rovka, hiraditya, volkan, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74950
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir |
 | llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp |
Commit
9fff6e823cf79075d1f386e1e875b73405368620
by mcinally[AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll
Add +fullfp16 to sve-vector-splat.ll so we can test folding of immediates into moves.
This attribute can go away later when SVE has a full set of fp16 patterns in place.
Differential Revision: https://reviews.llvm.org/D74965
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 | llvm/test/CodeGen/AArch64/sve-vector-splat.ll |
Commit
134bab7cd5679673d6807595ae77b5bc0c3b83c2
by flo[DSE,MSSA] Add debug counter.
Can be used like -debug-counter=dse-memoryssa-skip=10,dse-memoryssa-counter-count=20
Reviewers: dmgreen, rnk, efriedma, bryant, asbirlea
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D72147
|
 | llvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll |
 | llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp |
Commit
23444edf30ba00ccefa3a582ac7ddc29774e9da5
by yitzhakm[AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls.
Summary: This revision adds matchers that match calls to the gtest EXPECT and ASSERT macros almost like function calls. The matchers are placed in separate files (GtestMatchers...), because they are specific to the gtest library.
Reviewers: gribozavr2
Subscribers: mgorny, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74840
|
 | clang/unittests/ASTMatchers/CMakeLists.txt |
 | clang/lib/ASTMatchers/GtestMatchers.cpp |
 | clang/include/clang/ASTMatchers/GtestMatchers.h |
 | clang/unittests/ASTMatchers/GtestMatchersTest.cpp |
 | clang/lib/ASTMatchers/CMakeLists.txt |
Commit
fc4455891c00bfa16c85d0cebe6158fafe11667d
by spatel[VectorCombine] refactor matching code to reduce duplication; NFC
cmp/binop were already diverging even though they are largely the same logic.
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 | llvm/lib/Transforms/Vectorize/VectorCombine.cpp |
Commit
db9c40f5624e6d55e0cbafe3f3980a7223e197c4
by danilo.carvalho.grael[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations
Summary: Add intrinsics for the following operations: - eor3, bcax - bsl, bsl1n, bsl2n, nbsl
Fix MC tests for bsl instructions.
Reviewers: kmclaughlin, c-rhodes, sdesmalen, efriedma, rengolin
Reviewed By: efriedma
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74785
|
 | llvm/include/llvm/IR/IntrinsicsAArch64.td |
 | llvm/lib/Target/AArch64/SVEInstrFormats.td |
 | llvm/test/MC/AArch64/SVE2/nbsl-diagnostics.s |
 | llvm/test/CodeGen/AArch64/sve2-bitwise-ternary.ll |
 | llvm/test/MC/AArch64/SVE2/bsl2n-diagnostics.s |
 | llvm/test/MC/AArch64/SVE2/bsl1n-diagnostics.s |
 | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td |
 | llvm/test/MC/AArch64/SVE2/bsl-diagnostics.s |
Commit
60023e347116e5004295e8c7f2f09cc1855d4d84
by arsenm2AMDGPU: Use default operand for VOP3P clamp
We don't use this, and matching from the def doesn't make much sense.
There are multiple tablegen bugs with default operand handling. undef_tied_input should work to handle the vdst_in correctly, but this breaks the operand register class constraint which it should be able to infer.
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 | llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
 | llvm/lib/Target/AMDGPU/VOP3PInstructions.td |
 | llvm/lib/Target/AMDGPU/SIInstrInfo.td |
 | llvm/lib/Target/AMDGPU/VOP3Instructions.td |
Commit
41bd9ead35f60823c59367efe4f3d5ade87e756d
by paulsson[SystemZ] Return scalarized costs for vector instructions on older archs.
A cost query for a vector instruction should return a cost even without target vector support, and not trigger an assert.
VectorCombine does this with an input containing source code vectors.
Review: Ulrich Weigand
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 | llvm/test/Analysis/CostModel/SystemZ/oldarch-vectors.ll |
 | llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp |
Commit
8c70a2597f53457efc8eb2798c1d1056bb105ec3
by llvmgnsyncbot[gn build] Port 23444edf30b
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 | llvm/utils/gn/secondary/clang/lib/ASTMatchers/BUILD.gn |
 | llvm/utils/gn/secondary/clang/unittests/ASTMatchers/BUILD.gn |
Commit
a8db806d52ce02ddca179b811da164023316d4b9
by nikita.ppv[SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls
This changes the SimplifyLibCalls utility to accept an IRBuilderBase, which allows us to pass through the IRBuilder used by InstCombine. This will ensure that new instructions get added to the worklist. The annotated test-case drops from 4 to 2 InstCombine iterations thanks to this.
To achieve this, I'm adding an IRBuilderBase::OperandBundlesGuard, which is basically the same as the existing InsertPointGuard and FastMathFlagsGuard, but for operand bundles. Also add a setDefaultOperandBundles() method so these can be set outside the constructor.
Differential Revision: https://reviews.llvm.org/D74792
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 | llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp |
 | llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp |
 | llvm/lib/CodeGen/CodeGenPrepare.cpp |
 | llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h |
 | llvm/include/llvm/IR/IRBuilder.h |
 | llvm/test/Transforms/InstCombine/simplify-libcalls.ll |
Commit
c90ea87cfd71f8da05f2e684d3cf139f9773c15d
by nikita.ppv[X86] Fix SDLoc initialization
Fixes -Wparentheses warning, in this case indicating a genuine bug.
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 | llvm/lib/Target/X86/X86ISelLowering.cpp |
Commit
98f5268a7292c2996e2f718382e2d5404eb5d112
by flo[VectorUtils] Move ToVectorTy to VectorUtils.h (NFC).
ToVectorTy is defined and used in multiple places. Hoist it to VectorUtils.h to avoid duplication and improve re-usability.
Reviewers: rengolin, hsaito, Ayal, gilr, fpetrogalli
Reviewed By: fpetrogalli
Differential Revision: https://reviews.llvm.org/D74959
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 | llvm/include/llvm/Analysis/VectorUtils.h |
 | llvm/lib/Transforms/Utils/InjectTLIMappings.cpp |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
Commit
deb0a8bfc4923356beaa47b960d14b0c46a14721
by flo[DSE,MSSA] Dbg counters required assertions. Mark test accordingly.
|
 | llvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll |
Commit
656dff9af48bd242fc0f8a20cf50c6d0921df052
by nikita.ppv[InstCombine] Use replaceOperand() in more places
Followup to D73919 with another batch of replacements of setOperand() -> replaceOperand(), to make sure the old operand gets DCEd right away.
Differential Revision: https://reviews.llvm.org/D74932
|
 | llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp |
 | llvm/lib/Transforms/InstCombine/InstructionCombining.cpp |
Commit
e4df934ca7b408cfb52531016198545a8d50f41a
by maskray[Clang interpreter] Rename Block.{h,cpp} to InterpBlock.{h,cpp}
The Blocks runtime provide a header named Block.h. It is generally preferable to avoid name collision with system headers (reducing reliance on -isystem order, more friendly when navigating files in an editor, etc).
Reviewed By: gribozavr2
Differential Revision: https://reviews.llvm.org/D74934
|
 | clang/lib/AST/Interp/InterpBlock.cpp |
 | clang/lib/AST/CMakeLists.txt |
 | llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn |
 | clang/lib/AST/Interp/Block.cpp |
 | clang/lib/AST/Interp/Block.h |
 | clang/lib/AST/Interp/InterpBlock.h |
 | clang/lib/AST/Interp/Pointer.cpp |
 | clang/lib/AST/Interp/Pointer.h |
Commit
0e3e242209c7f84009c9d88fe52982f8ba21c68b
by yamauchi[BFI] Fix missed BFI updates in MachineSink.
Summary: This prevents BFI queries on new blocks (from MachineSinking::GetAllSortedSuccessors) and fixes a bunch of assert failures under -check-bfi-unknown-block-queries=true.
Reviewers: davidxl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74511
|
 | llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp |
 | llvm/include/llvm/CodeGen/MachineBlockFrequencyInfo.h |
 | llvm/lib/CodeGen/MachineSink.cpp |
 | llvm/test/CodeGen/X86/machine-sink.ll |
Commit
b178555318cdccecc9d3fb4af89b4a765cb0e48c
by nikita.ppv[InstCombine] Improve simplify demanded bits worklist management
This fixes a small mistake from D72944: The worklist add should happen before assigning the new operand, not after.
In case an actual replacement happens, the old operand needs to be added for DCE. If no actual replacement happens, then old/new are the same, so it doesn't matter.
This drops one iteration from the annotated test case.
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 | llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp |
 | llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll |
Commit
31ec721516b5ed36f7dbed180a903e269f29716d
by francesco.petrogalli[llvm][CodeGen] DAG Combiner folds for vscale.
Summary: This patch simplifies the DAGs generated when using the intrinsic `@llvm.vscale.*` as follows:
* Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)). * Canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C)). * Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)). * Fold (shl (vscale * C0), C1) to (vscale * (C0 << C1)).
The test `sve-gep-ll` have been updated to reflect the folding introduced by this patch.
Reviewers: efriedma, sdesmalen, andwar, rengolin
Reviewed By: sdesmalen
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74782
|
 | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp |
 | llvm/test/CodeGen/AArch64/sve-gep.ll |
 | llvm/test/CodeGen/AArch64/sve-vscale-combine.ll |
Commit
bc7b26c333f51b4b534abb81d597c0b86123718c
by diego.caballero[MLIR] Allow Loop dialect IfOp and ForOp to define values
This patch implements the RFCs proposed here: https://llvm.discourse.group/t/rfc-modify-ifop-in-loop-dialect-to-yield-values/463 https://llvm.discourse.group/t/rfc-adding-operands-and-results-to-loop-for/459/19.
It introduces the following changes: - All Loop Ops region, except for ReduceOp, terminate with a YieldOp. - YieldOp can have variadice operands that is used to return values out of IfOp and ForOp regions. - Change IfOp and ForOp syntax and representation to define values. - Add unit-tests and update .td documentation. - YieldOp is a terminator to loop.for/if/parallel - YieldOp custom parser and printer
Lowering is not supported at the moment, and will be in a follow-up PR.
Thanks.
Reviewed By: bondhugula, nicolasvasilache, rriddle
Differential Revision: https://reviews.llvm.org/D74174
|
 | mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp |
 | mlir/test/Conversion/LoopsToGPU/parallel_loop.mlir |
 | mlir/include/mlir/Dialect/LoopOps/LoopOps.td |
 | mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp |
 | mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp |
 | mlir/lib/Dialect/LoopOps/LoopOps.cpp |
 | mlir/test/Dialect/Loops/invalid.mlir |
 | mlir/test/Dialect/Loops/parallel-loop-fusion.mlir |
 | mlir/include/mlir/IR/OpImplementation.h |
 | mlir/test/Dialect/Loops/ops.mlir |
 | mlir/lib/Parser/Parser.cpp |
 | mlir/test/Dialect/Linalg/parallel_loops.mlir |
 | mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp |
Commit
6b4a193defbe59b2b93e9d0289b2a7d9c2d842b9
by jasonliu[XCOFF][AIX] Put undefined symbol name into StringTable when neccessary
Summary: When we have a long name for the undefined symbol, we would hit this assertion: Assertion failed: I != StringIndexMap.end() && "String is not in table!" This patch addresses that.
Reviewed by: DiggerLin, daltenty
Differential Revision: https://reviews.llvm.org/D74924
|
 | llvm/lib/MC/XCOFFObjectWriter.cpp |
 | llvm/test/CodeGen/PowerPC/aix-undef-func-call.ll |
Commit
2769fb90f0a4e6178306b521c5e79708b16de1fc
by llvm-dev[LoopVectorize][X86] Regenerate tests. NFCI.
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 | llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll |
 | llvm/test/Transforms/LoopVectorize/X86/interleaving.ll |
Commit
1723f219939e1d4dc1c53ec7caf10c9380822b99
by llvm-devFix MSVC "not all control paths return a value" warning. NFCI.
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 | clang/lib/ASTMatchers/GtestMatchers.cpp |
Commit
72eef820d528ab93982e54cd49c44fabf20e83a5
by arsenm2AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR
G_SHUFFLE_VECTOR is legal since it theoretically may help match op_sel for VOP3P instructions. Expand it in some other way in case it doesn't fold into the use instructions.
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 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h |
 | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |
Commit
dfce5fd50a00110890ad95dacca75886c6fd456d
by arsenm2AMDGPU/GlobalISel: Select VOP3P instructions
This only handles the basic cases. More work is needed to make better use of op_sel.
|
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUGISel.td |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir |
Commit
4c1c9422a3adab64433b8fde31f1ac346459b491
by arsenm2AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2
I'm slighly worried about the generated checks, since they won't catch incorrect modifiers being added at the end of the line.
|
 | llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll |
 | llvm/lib/Target/AMDGPU/VOP3PInstructions.td |
Commit
db06870dbd5e85acbd39bb8dc3b2e1c751904f86
by arsenm2AMDGPU: Move dot intrinsic patterns to instruction def
I tried to use some of the new tablegen features to avoid creating different operand list permutations, but I still don't see a way to programmatically build a source pattern dag.
Also add GlobalISel tests, which now all import successfully.
Some of the fneg fold tests are incorrect, which need to be fixed in a future commit
|
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll |
 | llvm/lib/Target/AMDGPU/VOP3Instructions.td |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll |
 | llvm/lib/Target/AMDGPU/VOP3PInstructions.td |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll |
Commit
07d2cdae11633139947f105888163adfd5646ce7
by nullptr[lldb/cmake] Enable more verbose find_package output.
Summary: The purpose of this patch is to make identifying missing dependencies clearer to the user. `find_package` will report if a package is not found, that output, combined with the exiting status message, is clearer than not having the additional verbosity.
If the SWIG dependency is required {LLDB_ENABLE_PYTHON, LLDB_ENABLE_LUA} and SWIG is not available, fail the configuration step. Terminate the configure early rather than later with a clear error message.
We could possibly modify: `llvm-project/lldb/cmake/modules/FindPythonInterpAndLibs.cmake` However, the patch here seems clear in my opinion.
Reviewers: aadsm, hhb, JDevlieghere
Reviewed By: JDevlieghere
Subscribers: labath, jrm, mgorny, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D74917
|
 | lldb/cmake/modules/FindLuaAndSwig.cmake |
 | lldb/cmake/modules/FindPythonInterpAndLibs.cmake |
Commit
00955a62e4333c7ca889043d6a9033cb8cbf800d
by arsenm2AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max
The legalizer helper functions are unusably awkward to perform the 3-5 part legalization. This needs to be widened, scalarized, lowered, and we should avoid creating vector extends and truncates. Manually do all of this and expand.
|
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir |
 | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
Commit
73d8d83a6d9adac3216ea8a39eb502b2a5c4d083
by maskray[ARM] Change ARMAttributeParser::Parse to use support::endianness and simplify
|
 | llvm/tools/llvm-readobj/ELFDumper.cpp |
 | llvm/unittests/Support/ARMAttributeParser.cpp |
 | llvm/include/llvm/Object/ELFObjectFile.h |
 | llvm/lib/Support/ARMAttributeParser.cpp |
 | lld/ELF/InputFiles.cpp |
 | llvm/include/llvm/Support/ARMAttributeParser.h |
Commit
7dd6a862e5ece866c787d4509a5a5cad19531fbc
by Louis Dionne[libc++] Do not set the `availability=XXX` feature when not testing against a system libc++
Otherwise, the `availability=XXX` lit feature is set even when we're testing trunk and _LIBCPP_DISABLE_AVAILABILITY is defined, which causes tests that check for availability markup to be enabled and unexpectedly pass.
|
 | libcxx/utils/libcxx/test/config.py |
Commit
266959c0f72ff359a60fe43da0cf336604611029
by mcinally[AArch64][SVE] Add backend support for splats of immediates
This patch adds backend support for splats of both Int and FP immediates.
Differential Revision: https://reviews.llvm.org/D74856
|
 | llvm/test/CodeGen/AArch64/sve-vector-splat.ll |
 | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td |
 | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp |
Commit
0781e93a6eaa71ec5d87be3bbeeeed053067f7ee
by luismarques[CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V
By default the RISC-V target doesn't have the atomics standard extension enabled. The first RUN line in `clang/test/CodeGen/atomic_ops.c` didn't specify a target triple, which meant that on RISC-V Linux hosts it would target RISC-V, but because it used clang cc1 we didn't get the toolchain driver functionality to automatically turn on the extensions implied by the target triple (riscv64-linux includes atomics). This would cause the test to fail on RISC-V hosts.
This patch changes the test to have RUN lines for two explicit targets, one with native atomics and one without. To work around FileCheck limitations and more accurately match the output, some tests now have separate prefixes for the two cases.
Reviewers: jyknight, eli.friedman, lenary, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D74847
|
 | clang/test/CodeGen/atomic_ops.c |
Commit
29ad9d6b26ee92c7843c06392625d894d58658c2
by hanchung[mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V.
Differential Revision: https://reviews.llvm.org/D74874
|
 | mlir/test/Conversion/StandardToSPIRV/std-to-spirv.mlir |
 | mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp |
 | mlir/test/Dialect/SPIRV/Serialization/memory-ops.mlir |
Commit
042d97eda9fabbf7718e32fc5efe9150c7d8bfa9
by diego.caballero[MLIR] Remove constexpr from LoopOps.td
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D74978
|
 | mlir/include/mlir/Dialect/LoopOps/LoopOps.td |
Commit
d2b7c09e79a12cb61fc424429b348b2c04364d07
by kparzysz[Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q if possible
When each byte in b&m is non-zero, this conversion Q->V->Q is a no-op.
|
 | llvm/test/Transforms/InstCombine/Hexagon/simplify-hvx-qvq.ll |
 | llvm/test/Transforms/InstCombine/Hexagon/lit.local.cfg |
 | llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp |
Commit
69d757c0e8ffc5b49fda10df38e470a56d616ef4
by riddleriverMove StandardOps/Ops.h to StandardOps/IR/Ops.h
Summary: NFC - Moved StandardOps/Ops.h to a StandardOps/IR dir to better match surrounding directories. This is to match other dialects, and prepare for moving StandardOps related transforms in out for Transforms and into StandardOps/Transforms.
Differential Revision: https://reviews.llvm.org/D74940
|
 | mlir/test/lib/Transforms/TestMemRefDependenceCheck.cpp |
 | mlir/lib/Analysis/NestedMatcher.cpp |
 | mlir/include/mlir/Dialect/StandardOps/EDSC/Builders.h |
 | mlir/lib/Dialect/VectorOps/VectorOps.cpp |
 | mlir/include/mlir/Dialect/StandardOps/IR/Ops.h |
 | mlir/lib/Transforms/AffineLoopInvariantCodeMotion.cpp |
 | mlir/lib/Analysis/AffineStructures.cpp |
 | mlir/lib/Transforms/LoopCoalescing.cpp |
 | mlir/lib/Dialect/QuantOps/Transforms/ConvertConst.cpp |
 | mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp |
 | mlir/test/lib/DeclarativeTransforms/TestVectorTransformPatterns.td |
 | mlir/include/mlir/Dialect/StandardOps/Ops.td |
 | mlir/lib/Transforms/Vectorize.cpp |
 | mlir/test/lib/Transforms/TestVectorTransforms.cpp |
 | mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp |
 | mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp |
 | mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp |
 | mlir/lib/Transforms/PipelineDataTransfer.cpp |
 | mlir/lib/Dialect/VectorOps/VectorTransforms.cpp |
 | mlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp |
 | mlir/lib/Conversion/LoopsToGPU/LoopsToGPUPass.cpp |
 | mlir/lib/Dialect/StandardOps/IR/Ops.cpp |
 | mlir/include/mlir/Dialect/StandardOps/CMakeLists.txt |
 | mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp |
 | mlir/test/lib/Transforms/TestConstantFold.cpp |
 | mlir/lib/Dialect/LoopOps/Transforms/ParallelLoopFusion.cpp |
 | mlir/lib/Quantizer/Configurations/FxpMathConfig.cpp |
 | mlir/lib/Dialect/StandardOps/CMakeLists.txt |
 | mlir/include/mlir/Dialect/StandardOps/IR/Ops.td |
 | mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h |
 | mlir/lib/Conversion/LoopToStandard/ConvertLoopToStandard.cpp |
 | mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp |
 | mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp |
 | mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp |
 | mlir/lib/Transforms/Utils/LoopFusionUtils.cpp |
 | mlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp |
 | mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.td |
 | mlir/lib/Dialect/AffineOps/AffineOps.cpp |
 | mlir/lib/Dialect/GPU/IR/GPUDialect.cpp |
 | mlir/include/mlir/Dialect/Linalg/EDSC/Builders.h |
 | mlir/include/mlir/InitAllDialects.h |
 | mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp |
 | mlir/lib/Dialect/Linalg/Utils/Utils.cpp |
 | mlir/lib/Analysis/AffineAnalysis.cpp |
 | mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp |
 | mlir/lib/Transforms/LoopFusion.cpp |
 | mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp |
 | mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp |
 | mlir/lib/Transforms/MemRefDataFlowOpt.cpp |
 | mlir/include/mlir/Transforms/Utils.h |
 | mlir/include/mlir/Dialect/StandardOps/IR/CMakeLists.txt |
 | mlir/lib/Dialect/StandardOps/Ops.cpp |
 | mlir/lib/Analysis/Utils.cpp |
 | mlir/lib/Transforms/Utils/FoldUtils.cpp |
 | mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp |
 | mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp |
 | mlir/test/lib/Transforms/TestLoopFusion.cpp |
 | mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp |
 | mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp |
 | mlir/test/lib/Transforms/TestOpaqueLoc.cpp |
 | mlir/test/lib/Transforms/TestInlining.cpp |
 | mlir/include/mlir/Dialect/Linalg/Utils/Utils.h |
 | mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp |
 | mlir/include/mlir/Dialect/StandardOps/Ops.h |
 | mlir/lib/Transforms/Utils/Utils.cpp |
 | mlir/lib/Dialect/LoopOps/LoopOps.cpp |
 | mlir/lib/Dialect/VectorOps/VectorUtils.cpp |
 | mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp |
 | mlir/test/lib/IR/TestMatchers.cpp |
 | mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp |
Commit
e2ed1d14d6c2d11d1a5df23bd679bcb7e6cbf433
by francesco.petrogalli[llvm][aarch64] SVE addressing modes.
Summary: Added register + immediate and register + register addressing modes for the following intrinsics:
1. Masked load and stores: * Sign and zero extended load and truncated stores. * No extension or truncation. 2. Masked non-temporal load and store.
Reviewers: andwar, efriedma
Subscribers: cameron.mcinally, sdesmalen, tschuett, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74254
|
 | llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll |
 | llvm/lib/Target/AArch64/SVEInstrFormats.td |
 | llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll |
 | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp |
 | llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll |
 | llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll |
 | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td |
Commit
34e3485560cbe8b0e843a1a9ef0cf796e6a4e237
by spatel[VectorCombine] refactor cost calcs to reduce duplication; NFC
More cleanup is possible now, but we probably need to resolve the TODO about the existing difference between compares and binops.
|
 | llvm/lib/Transforms/Vectorize/VectorCombine.cpp |
Commit
33bf1196475cbc9b84914c41308cf252764803ee
by francesco.petrogalli[llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE.
Summary: The patch covers both register/register and register/immediate addressing modes.
Reviewers: efriedma, andwar, sdesmalen
Reviewed By: sdesmalen
Subscribers: sdesmalen, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74581
|
 | llvm/include/llvm/IR/IntrinsicsAArch64.td |
 | llvm/lib/Target/AArch64/SVEInstrFormats.td |
 | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td |
 | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp |
 | llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll |
Commit
446b150065c331daa82a9f5436f4987e340e5d6f
by rnk[IR] Update BasicBlock::validateInstrOrdering comments, NFC
Pointed out by Jay Foad.
|
 | llvm/include/llvm/IR/BasicBlock.h |
 | llvm/lib/IR/BasicBlock.cpp |
Commit
8875ee18d72b1b395331c1b7217d2b91fb4dc4b7
by craig.topper[X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix.
isPrefix was added to support the patches to align branches. it relies on a switch over instruction names.
This moves those opcodes to a new format so the information is tablegen and we can just check for a specific value in some bits in TSFlags instead.
I've left the other function in place for now so that the existing patches in phabricator will still work. I'll work with the owner to get them migrated.
|
 | llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h |
 | llvm/lib/Target/X86/X86InstrTSX.td |
 | llvm/lib/Target/X86/X86InstrFormats.td |
 | llvm/lib/Target/X86/X86InstrSystem.td |
 | llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp |
 | llvm/lib/Target/X86/X86InstrInfo.td |
 | llvm/tools/llvm-exegesis/lib/X86/Target.cpp |
 | llvm/utils/TableGen/X86RecognizableInstr.h |
 | llvm/utils/TableGen/X86RecognizableInstr.cpp |
Commit
1874dee5662603c9251228c71b66de72cec0c979
by francisvm[macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat
This moves all the logic of converting LLVM Triples to MachO::CPU_(SUB_)TYPE from the specific target (Target)AsmBackend to more convenient functions in lib/BinaryFormat.
This also gets rid of the separate two X86AsmBackend classes.
The previous attempt was to add it to libObject, but that adds an unnecessary dependency to libObject from all the targets.
Differential Revision: https://reviews.llvm.org/D74808
|
 | llvm/lib/BinaryFormat/MachO.cpp |
 | llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp |
 | llvm/lib/BinaryFormat/CMakeLists.txt |
 | llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp |
 | llvm/include/llvm/BinaryFormat/MachO.h |
 | llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp |
 | llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h |
 | llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp |
 | llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp |
Commit
0bb90628b5f7c170689d2d3f019af773772fc649
by hhbAllow customized relative PYTHONHOME
Summary: This change allows a hard coded relative PYTHONHOME setting. So that python can easily be packaged together with lldb.
The change includes: 1. Extend LLDB_RELOCATABLE_PYTHON to all platforms. It defaults to ON for platforms other than Windows, to keep the behavior compatible. 2. Allows to customize LLDB_PYTHON_HOME. But still defaults to PYTHON_HOME. 3. LLDB_PYTHON_HOME can be a path relative to liblldb. If it is relative, we will resolve it before send it to Py_DecodeLocale.
Subscribers: mgorny, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D74727
|
 | lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp |
 | lldb/cmake/modules/LLDBConfig.cmake |
 | lldb/include/lldb/Host/Config.h.cmake |
Commit
8fa776b8ed02f36e6bc072c6748725890dfadcbe
by llvmgnsyncbot[gn build] Port 1874dee5662
|
 | llvm/utils/gn/secondary/llvm/lib/BinaryFormat/BUILD.gn |
Commit
e9c79a7aef19b14e68ed50eb9382856e9453c5a0
by spatel[VectorCombine] refactor to reduce duplicated code; NFC
This should be the last step in the current cleanup. Follow-ups should resolve the TODO about cost calc and enable the more general case where we extract different elements.
|
 | llvm/lib/Transforms/Vectorize/VectorCombine.cpp |
Commit
b72f1448ce42f4e38f0c2a33418089f2320ab8f3
by jay.foadAMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74987
|
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir |