FailedChanges

Summary

  1. AMDGPU/GlobalISel: Fix constant bus violation with source modifiers (details)
  2. AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy (details)
  3. AMDGPU/GlobalISel: Legalize G_FPOW (details)
  4. AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC (details)
  5. [ARM] Correct Formatting. NFC (details)
  6. AMDGPU/GlobalISel: Precommit xnor matching test (details)
  7. [ELF] Ignore the maximum of input section alignments for two cases (details)
  8. [ELF] Warn changed output section address (details)
  9. [lldb-vscode] Use libOption with tablegen to parse command line options. (details)
  10. [ELF] Shuffle .init_array/.fini_array with --shuffle-sections= (details)
  11. [TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls. (details)
  12. AMDGPU/GlobalISel: Fix xnor matching (details)
  13. AMDGPU/GlobalISel: Commit test changes I forgot to squash (details)
  14. GlobalISel: Fix narrowing of (G_ASHR i64:x, 32) (details)
  15. [AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll (details)
  16. [DSE,MSSA] Add debug counter. (details)
  17. [AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls. (details)
  18. [VectorCombine] refactor matching code to reduce duplication; NFC (details)
  19. [AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations (details)
  20. AMDGPU: Use default operand for VOP3P clamp (details)
  21. [SystemZ]  Return scalarized costs for vector instructions on older archs. (details)
  22. [gn build] Port 23444edf30b (details)
  23. [SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls (details)
  24. [X86] Fix SDLoc initialization (details)
  25. [VectorUtils] Move ToVectorTy to VectorUtils.h (NFC). (details)
  26. [DSE,MSSA] Dbg counters required assertions. Mark test accordingly. (details)
  27. [InstCombine] Use replaceOperand() in more places (details)
  28. [Clang interpreter] Rename Block.{h,cpp} to InterpBlock.{h,cpp} (details)
  29. [BFI] Fix missed BFI updates in MachineSink. (details)
  30. [InstCombine] Improve simplify demanded bits worklist management (details)
  31. [llvm][CodeGen] DAG Combiner folds for vscale. (details)
  32. [MLIR] Allow Loop dialect IfOp and ForOp to define values (details)
  33. [XCOFF][AIX] Put undefined symbol name into StringTable when neccessary (details)
  34. [LoopVectorize][X86] Regenerate tests. NFCI. (details)
  35. Fix MSVC "not all control paths return a value" warning. NFCI. (details)
  36. AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR (details)
  37. AMDGPU/GlobalISel: Select VOP3P instructions (details)
  38. AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2 (details)
  39. AMDGPU: Move dot intrinsic patterns to instruction def (details)
  40. [lldb/cmake] Enable more verbose find_package output. (details)
  41. AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max (details)
  42. [ARM] Change ARMAttributeParser::Parse to use support::endianness and simplify (details)
  43. [libc++] Do not set the `availability=XXX` feature when not testing against a system libc++ (details)
  44. [AArch64][SVE] Add backend support for splats of immediates (details)
  45. [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V (details)
  46. [mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V. (details)
  47. [MLIR] Remove constexpr from LoopOps.td (details)
  48. [Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q if possible (details)
  49. Move StandardOps/Ops.h to StandardOps/IR/Ops.h (details)
  50. [llvm][aarch64] SVE addressing modes. (details)
  51. [VectorCombine] refactor cost calcs to reduce duplication; NFC (details)
  52. [llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE. (details)
  53. [IR] Update BasicBlock::validateInstrOrdering comments, NFC (details)
  54. [X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix. (details)
  55. [macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat (details)
  56. Allow customized relative PYTHONHOME (details)
  57. [gn build] Port 1874dee5662 (details)
  58. [VectorCombine] refactor to reduce duplicated code; NFC (details)
  59. AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16 (details)
Commit b64aa8c715112ac4b9fd1ae8eb5ecb981ecd091a by arsenm2
AMDGPU/GlobalISel: Fix constant bus violation with source modifiers

This looked through copies to find the source modifiers, which may
have been SGPR->VGPR copies added to avoid potential constant bus
violations. Re-insert a copy to a VGPR if this happens.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit fab4cdea3911b19d1b1819102aee0252cbd4eba4 by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
Commit 79ff188addeeea127c7a7edd808c5821917d4bb6 by arsenm2
AMDGPU/GlobalISel: Legalize G_FPOW

There are few differences from the DAG handling. First, the DAG
handling uses a primitive selection pattern instead of custom
legalizing it. Because of this, this makes use of source modifiers
while the DAG does not.

Also instead of promoting f16, try to use the f16 log/exp. There's no
f16 fmul_legacy, so widen just for the multiply, although I'm not sure
that's the best solution.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
Commit ac7abe0ba9ae4c6a2248cc3ef4e4fe7e6d270105 by arsenm2
AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC

We have patterns for s_pack* selection, but they assume the inputs are
a build_vector with 16-bit inputs, not a truncating build
vector. Since there's still outstanding work for how to handle
mismatched result and source element vector operations, and since I'm
trying a different packed vector strategy than SelectionDAG, just
manually select this for now.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 83012cb217189bb6faa1256cc44fd0c306363264 by david.green
[ARM] Correct Formatting. NFC

Also removed an unnecessary TODO that I don't believe is relevant for
the instruction in question.
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 89dc8fe6222041319e073ceb8ee0cb38d045ea16 by arsenm2
AMDGPU/GlobalISel: Precommit xnor matching test
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
Commit 6ed8e2014330b6a48d238cdc4357e788cdd6d445 by maskray
[ELF] Ignore the maximum of input section alignments for two cases

Follow-up for D74286.

Notations:

* alignExpr: the computed ALIGN value
* max_input_align: the maximum of input section alignments

This patch changes the following two cases to match GNU ld:

* When ALIGN is present, GNU ld sets output sh_addr to alignExpr, while lld use max(alignExpr, max_input_align)
* When addrExpr is specified but alignExpr is not, GNU ld sets output sh_addr to addrExpr, while lld uses `advance(0, max_input_align)`

Note, sh_addralign is still set to max(alignExpr, max_input_align).

lma-align.test is enhanced a bit to check we don't overalign sh_addr.

fixSectionAlignments() sets addrExpr but not alignExpr for the `!hasSectionsCommand` case.
This patch sets alignExpr as well so that max_input_align will be respected.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74736
The file was addedlld/test/ELF/linkerscript/section-align2.test
The file was modifiedlld/test/ELF/linkerscript/outsections-addr.s
The file was modifiedlld/test/ELF/linkerscript/lma-align.test
The file was modifiedlld/ELF/LinkerScript.cpp
The file was modifiedlld/ELF/Writer.cpp
Commit de0dda54d38137d0714c279a540074fe73822b8b by maskray
[ELF] Warn changed output section address

When the output section address (addrExpr) is specified, GNU ld warns if
sh_addr is different. This patch implements the warning.

Note, LinkerScript::assignAddresses can be called more than once. We
need to record the changed section addresses, and only report the
warnings after the addresses are finalized.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74741
The file was modifiedlld/ELF/Writer.cpp
The file was modifiedlld/test/ELF/linkerscript/lma-align.test
The file was modifiedlld/ELF/LinkerScript.h
The file was modifiedlld/ELF/LinkerScript.cpp
The file was modifiedlld/test/ELF/linkerscript/section-align2.test
Commit c47e0e2d37d32ec56c760f1a2c9740d69c370b57 by Jonas Devlieghere
[lldb-vscode] Use libOption with tablegen to parse command line options.

This change will bring lldb-vscode in line with how several other llvm
tools process command line arguments and make it easier to add future
options.

Differential revision: https://reviews.llvm.org/D74798
The file was addedlldb/tools/lldb-vscode/Options.td
The file was modifiedlldb/tools/lldb-vscode/CMakeLists.txt
The file was modifiedlldb/tools/lldb-vscode/lldb-vscode.cpp
The file was modifiedlldb/test/Shell/helper/toolchain.py
The file was addedlldb/test/Shell/VSCode/TestOptions.test
Commit dbd7281aa775a0e23c43a02583593900cd4c05be by maskray
[ELF] Shuffle .init_array/.fini_array with --shuffle-sections=

Useful for detecting static initialization order fiasco.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74887
The file was addedlld/test/ELF/shuffle-sections-init-fini.s
The file was modifiedlld/ELF/Writer.cpp
Commit 42ec6fdce92090c02a10506fbdb2257fdbc2d1fd by llvm-dev
[TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls.

Minor refactor/cleanup before we begin adding non-uniform support.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 043ed2e22ac442c2116f5df6367d3889ea0b9de1 by arsenm2
AMDGPU/GlobalISel: Fix xnor matching

We should try the generated matchers before the manual selection. This
means the patterns are now handling the common cases, but the manual
selection code is not yet dead. It's still handling the non-s32/s64
cases (like v2s16 and v2s32). Currently tablegen doesn't have a nice
way to have a single pattern that covers multiple types.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
Commit 6a479220b5e8b25ec3ffe193c463cb3fdaac0e06 by arsenm2
AMDGPU/GlobalISel: Commit test changes I forgot to squash

These should have been in ac7abe0ba9ae4c6a2248cc3ef4e4fe7e6d270105
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
Commit cab39e4b8c826ec5dfebe17a18137272022e64ac by jay.foad
GlobalISel: Fix narrowing of (G_ASHR i64:x, 32)

Reviewers: arsenm

Subscribers: jvesely, wdng, nhaehnle, rovka, hiraditya, volkan, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74950
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
Commit 9fff6e823cf79075d1f386e1e875b73405368620 by mcinally
[AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll

Add +fullfp16 to sve-vector-splat.ll so we can test folding of immediates into moves.

This attribute can go away later when SVE has a full set of fp16 patterns in place.

Differential Revision: https://reviews.llvm.org/D74965
The file was modifiedllvm/test/CodeGen/AArch64/sve-vector-splat.ll
Commit 134bab7cd5679673d6807595ae77b5bc0c3b83c2 by flo
[DSE,MSSA] Add debug counter.

Can be used like
-debug-counter=dse-memoryssa-skip=10,dse-memoryssa-counter-count=20

Reviewers: dmgreen, rnk, efriedma, bryant, asbirlea

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D72147
The file was addedllvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Commit 23444edf30ba00ccefa3a582ac7ddc29774e9da5 by yitzhakm
[AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls.

Summary:
This revision adds matchers that match calls to the gtest EXPECT and ASSERT
macros almost like function calls. The matchers are placed in separate files
(GtestMatchers...), because they are specific to the gtest library.

Reviewers: gribozavr2

Subscribers: mgorny, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74840
The file was addedclang/lib/ASTMatchers/GtestMatchers.cpp
The file was modifiedclang/unittests/ASTMatchers/CMakeLists.txt
The file was addedclang/include/clang/ASTMatchers/GtestMatchers.h
The file was modifiedclang/lib/ASTMatchers/CMakeLists.txt
The file was addedclang/unittests/ASTMatchers/GtestMatchersTest.cpp
Commit fc4455891c00bfa16c85d0cebe6158fafe11667d by spatel
[VectorCombine] refactor matching code to reduce duplication; NFC

cmp/binop were already diverging even though they are largely
the same logic.
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit db9c40f5624e6d55e0cbafe3f3980a7223e197c4 by danilo.carvalho.grael
[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations

Summary:
Add intrinsics for the following operations:
- eor3, bcax
- bsl, bsl1n, bsl2n, nbsl

Fix MC tests for bsl instructions.

Reviewers: kmclaughlin, c-rhodes, sdesmalen, efriedma, rengolin

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74785
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl-diagnostics.s
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl1n-diagnostics.s
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl2n-diagnostics.s
The file was modifiedllvm/test/MC/AArch64/SVE2/nbsl-diagnostics.s
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve2-bitwise-ternary.ll
Commit 60023e347116e5004295e8c7f2f09cc1855d4d84 by arsenm2
AMDGPU: Use default operand for VOP3P clamp

We don't use this, and matching from the def doesn't make much sense.

There are multiple tablegen bugs with default operand
handling. undef_tied_input should work to handle the vdst_in
correctly, but this breaks the operand register class constraint which
it should be able to infer.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
Commit 41bd9ead35f60823c59367efe4f3d5ade87e756d by paulsson
[SystemZ]  Return scalarized costs for vector instructions on older archs.

A cost query for a vector instruction should return a cost even without
target vector support, and not trigger an assert.

VectorCombine does this with an input containing source code vectors.

Review: Ulrich Weigand
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
The file was addedllvm/test/Analysis/CostModel/SystemZ/oldarch-vectors.ll
Commit 8c70a2597f53457efc8eb2798c1d1056bb105ec3 by llvmgnsyncbot
[gn build] Port 23444edf30b
The file was modifiedllvm/utils/gn/secondary/clang/unittests/ASTMatchers/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/lib/ASTMatchers/BUILD.gn
Commit a8db806d52ce02ddca179b811da164023316d4b9 by nikita.ppv
[SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls

This changes the SimplifyLibCalls utility to accept an IRBuilderBase,
which allows us to pass through the IRBuilder used by InstCombine.
This will ensure that new instructions get added to the worklist.
The annotated test-case drops from 4 to 2 InstCombine iterations thanks
to this.

To achieve this, I'm adding an IRBuilderBase::OperandBundlesGuard,
which is basically the same as the existing InsertPointGuard and
FastMathFlagsGuard, but for operand bundles. Also add a
setDefaultOperandBundles() method so these can be set outside the
constructor.

Differential Revision: https://reviews.llvm.org/D74792
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/simplify-libcalls.ll
Commit c90ea87cfd71f8da05f2e684d3cf139f9773c15d by nikita.ppv
[X86] Fix SDLoc initialization

Fixes -Wparentheses warning, in this case indicating a genuine
bug.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 98f5268a7292c2996e2f718382e2d5404eb5d112 by flo
[VectorUtils] Move ToVectorTy to VectorUtils.h (NFC).

ToVectorTy is defined and used in multiple places. Hoist it to
VectorUtils.h to avoid duplication and improve re-usability.

Reviewers: rengolin, hsaito, Ayal, gilr, fpetrogalli

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D74959
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
The file was modifiedllvm/lib/Transforms/Utils/InjectTLIMappings.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit deb0a8bfc4923356beaa47b960d14b0c46a14721 by flo
[DSE,MSSA] Dbg counters required assertions. Mark test accordingly.
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll
Commit 656dff9af48bd242fc0f8a20cf50c6d0921df052 by nikita.ppv
[InstCombine] Use replaceOperand() in more places

Followup to D73919 with another batch of replacements of
setOperand() -> replaceOperand(), to make sure the old
operand gets DCEd right away.

Differential Revision: https://reviews.llvm.org/D74932
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit e4df934ca7b408cfb52531016198545a8d50f41a by maskray
[Clang interpreter] Rename Block.{h,cpp} to InterpBlock.{h,cpp}

The Blocks runtime provide a header named Block.h.
It is generally preferable to avoid name collision with system headers
(reducing reliance on -isystem order, more friendly when navigating files in
an editor, etc).

Reviewed By: gribozavr2

Differential Revision: https://reviews.llvm.org/D74934
The file was modifiedllvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
The file was addedclang/lib/AST/Interp/InterpBlock.cpp
The file was modifiedclang/lib/AST/CMakeLists.txt
The file was modifiedclang/lib/AST/Interp/Pointer.cpp
The file was removedclang/lib/AST/Interp/Block.h
The file was modifiedclang/lib/AST/Interp/Pointer.h
The file was removedclang/lib/AST/Interp/Block.cpp
The file was addedclang/lib/AST/Interp/InterpBlock.h
Commit 0e3e242209c7f84009c9d88fe52982f8ba21c68b by yamauchi
[BFI] Fix missed BFI updates in MachineSink.

Summary:
This prevents BFI queries on new blocks (from
MachineSinking::GetAllSortedSuccessors) and fixes a bunch of assert failures
under -check-bfi-unknown-block-queries=true.

Reviewers: davidxl

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74511
The file was modifiedllvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/machine-sink.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp
Commit b178555318cdccecc9d3fb4af89b4a765cb0e48c by nikita.ppv
[InstCombine] Improve simplify demanded bits worklist management

This fixes a small mistake from D72944: The worklist add should
happen before assigning the new operand, not after.

In case an actual replacement happens, the old operand needs to
be added for DCE. If no actual replacement happens, then old/new
are the same, so it doesn't matter.

This drops one iteration from the annotated test case.
The file was modifiedllvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Commit 31ec721516b5ed36f7dbed180a903e269f29716d by francesco.petrogalli
[llvm][CodeGen] DAG Combiner folds for vscale.

Summary:
This patch simplifies the DAGs generated when using the intrinsic `@llvm.vscale.*` as follows:

* Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
* Canonicalize (sub X, (vscale * C)) to (add X,  (vscale * -C)).
* Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)).
* Fold (shl (vscale * C0), C1) to (vscale * (C0 << C1)).

The test `sve-gep-ll` have been updated to reflect the folding introduced by this patch.

Reviewers: efriedma, sdesmalen, andwar, rengolin

Reviewed By: sdesmalen

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74782
The file was modifiedllvm/test/CodeGen/AArch64/sve-gep.ll
The file was addedllvm/test/CodeGen/AArch64/sve-vscale-combine.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit bc7b26c333f51b4b534abb81d597c0b86123718c by diego.caballero
[MLIR] Allow Loop dialect IfOp and ForOp to define values

This patch implements the RFCs proposed here:
https://llvm.discourse.group/t/rfc-modify-ifop-in-loop-dialect-to-yield-values/463
https://llvm.discourse.group/t/rfc-adding-operands-and-results-to-loop-for/459/19.

It introduces the following changes:
- All Loop Ops region, except for ReduceOp, terminate with a YieldOp.
- YieldOp can have variadice operands that is used to return values out of IfOp and ForOp regions.
- Change IfOp and ForOp syntax and representation to define values.
- Add unit-tests and update .td documentation.
- YieldOp is a terminator to loop.for/if/parallel
- YieldOp custom parser and printer

Lowering is not supported at the moment, and will be in a follow-up PR.

Thanks.

Reviewed By: bondhugula, nicolasvasilache, rriddle

Differential Revision: https://reviews.llvm.org/D74174
The file was modifiedmlir/include/mlir/Dialect/LoopOps/LoopOps.td
The file was modifiedmlir/test/Dialect/Loops/parallel-loop-fusion.mlir
The file was modifiedmlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
The file was modifiedmlir/test/Conversion/LoopsToGPU/parallel_loop.mlir
The file was modifiedmlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
The file was modifiedmlir/test/Dialect/Loops/ops.mlir
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/test/Dialect/Loops/invalid.mlir
The file was modifiedmlir/lib/Dialect/LoopOps/LoopOps.cpp
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/test/Dialect/Linalg/parallel_loops.mlir
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
Commit 6b4a193defbe59b2b93e9d0289b2a7d9c2d842b9 by jasonliu
[XCOFF][AIX] Put undefined symbol name into StringTable when neccessary

Summary:
When we have a long name for the undefined symbol, we would hit this assertion:
Assertion failed: I != StringIndexMap.end() && "String is not in table!"
This patch addresses that.

Reviewed by: DiggerLin, daltenty

Differential Revision: https://reviews.llvm.org/D74924
The file was modifiedllvm/lib/MC/XCOFFObjectWriter.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-undef-func-call.ll
Commit 2769fb90f0a4e6178306b521c5e79708b16de1fc by llvm-dev
[LoopVectorize][X86] Regenerate tests. NFCI.
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/interleaving.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
Commit 1723f219939e1d4dc1c53ec7caf10c9380822b99 by llvm-dev
Fix MSVC "not all control paths return a value" warning. NFCI.
The file was modifiedclang/lib/ASTMatchers/GtestMatchers.cpp
Commit 72eef820d528ab93982e54cd49c44fabf20e83a5 by arsenm2
AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR

G_SHUFFLE_VECTOR is legal since it theoretically may help match op_sel
for VOP3P instructions. Expand it in some other way in case it doesn't
fold into the use instructions.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
Commit dfce5fd50a00110890ad95dacca75886c6fd456d by arsenm2
AMDGPU/GlobalISel: Select VOP3P instructions

This only handles the basic cases. More work is needed to make better
use of op_sel.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
Commit 4c1c9422a3adab64433b8fde31f1ac346459b491 by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2

I'm slighly worried about the generated checks, since they won't catch
incorrect modifiers being added at the end of the line.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
Commit db06870dbd5e85acbd39bb8dc3b2e1c751904f86 by arsenm2
AMDGPU: Move dot intrinsic patterns to instruction def

I tried to use some of the new tablegen features to avoid creating
different operand list permutations, but I still don't see a way to
programmatically build a source pattern dag.

Also add GlobalISel tests, which now all import successfully.

Some of the fneg fold tests are incorrect, which need to be fixed in a
future commit
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
Commit 07d2cdae11633139947f105888163adfd5646ce7 by nullptr
[lldb/cmake] Enable more verbose find_package output.

Summary:
The purpose of this patch is to make identifying missing dependencies clearer to the user.
`find_package` will report if a package is not found, that output, combined with the exiting
status message, is clearer than not having the additional verbosity.

If the SWIG dependency is required {LLDB_ENABLE_PYTHON, LLDB_ENABLE_LUA}
and SWIG is not available, fail the configuration step.  Terminate the
configure early rather than later with a clear error message.

We could possibly modify:
`llvm-project/lldb/cmake/modules/FindPythonInterpAndLibs.cmake`
However, the patch here seems clear in my opinion.

Reviewers: aadsm, hhb, JDevlieghere

Reviewed By: JDevlieghere

Subscribers: labath, jrm, mgorny, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74917
The file was modifiedlldb/cmake/modules/FindPythonInterpAndLibs.cmake
The file was modifiedlldb/cmake/modules/FindLuaAndSwig.cmake
Commit 00955a62e4333c7ca889043d6a9033cb8cbf800d by arsenm2
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max

The legalizer helper functions are unusably awkward to perform the 3-5
part legalization. This needs to be widened, scalarized, lowered, and
we should avoid creating vector extends and truncates. Manually do all
of this and expand.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
Commit 73d8d83a6d9adac3216ea8a39eb502b2a5c4d083 by maskray
[ARM] Change ARMAttributeParser::Parse to use support::endianness and simplify
The file was modifiedllvm/include/llvm/Object/ELFObjectFile.h
The file was modifiedllvm/unittests/Support/ARMAttributeParser.cpp
The file was modifiedlld/ELF/InputFiles.cpp
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/include/llvm/Support/ARMAttributeParser.h
The file was modifiedllvm/lib/Support/ARMAttributeParser.cpp
Commit 7dd6a862e5ece866c787d4509a5a5cad19531fbc by Louis Dionne
[libc++] Do not set the `availability=XXX` feature when not testing against a system libc++

Otherwise, the `availability=XXX` lit feature is set even when we're
testing trunk and _LIBCPP_DISABLE_AVAILABILITY is defined, which causes
tests that check for availability markup to be enabled and unexpectedly
pass.
The file was modifiedlibcxx/utils/libcxx/test/config.py
Commit 266959c0f72ff359a60fe43da0cf336604611029 by mcinally
[AArch64][SVE] Add backend support for splats of immediates

This patch adds backend support for splats of both Int and FP immediates.

Differential Revision: https://reviews.llvm.org/D74856
The file was modifiedllvm/test/CodeGen/AArch64/sve-vector-splat.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 0781e93a6eaa71ec5d87be3bbeeeed053067f7ee by luismarques
[CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

By default the RISC-V target doesn't have the atomics standard extension
enabled. The first RUN line in `clang/test/CodeGen/atomic_ops.c` didn't
specify a target triple, which meant that on RISC-V Linux hosts it would
target RISC-V, but because it used clang cc1 we didn't get the toolchain
driver functionality to automatically turn on the extensions implied by
the target triple (riscv64-linux includes atomics). This would cause the
test to fail on RISC-V hosts.

This patch changes the test to have RUN lines for two explicit targets,
one with native atomics and one without. To work around FileCheck
limitations and more accurately match the output, some tests now have
separate prefixes for the two cases.

Reviewers: jyknight, eli.friedman, lenary, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D74847
The file was modifiedclang/test/CodeGen/atomic_ops.c
Commit 29ad9d6b26ee92c7843c06392625d894d58658c2 by hanchung
[mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V.

Differential Revision: https://reviews.llvm.org/D74874
The file was modifiedmlir/test/Dialect/SPIRV/Serialization/memory-ops.mlir
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVLowering.cpp
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-to-spirv.mlir
Commit 042d97eda9fabbf7718e32fc5efe9150c7d8bfa9 by diego.caballero
[MLIR] Remove constexpr from LoopOps.td

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D74978
The file was modifiedmlir/include/mlir/Dialect/LoopOps/LoopOps.td
Commit d2b7c09e79a12cb61fc424429b348b2c04364d07 by kparzysz
[Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q if possible

When each byte in b&m is non-zero, this conversion Q->V->Q is a no-op.
The file was addedllvm/test/Transforms/InstCombine/Hexagon/lit.local.cfg
The file was addedllvm/test/Transforms/InstCombine/Hexagon/simplify-hvx-qvq.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit 69d757c0e8ffc5b49fda10df38e470a56d616ef4 by riddleriver
Move StandardOps/Ops.h to StandardOps/IR/Ops.h

Summary:
NFC - Moved StandardOps/Ops.h to a StandardOps/IR dir to better match surrounding
directories. This is to match other dialects, and prepare for moving StandardOps
related transforms in out for Transforms and into StandardOps/Transforms.

Differential Revision: https://reviews.llvm.org/D74940
The file was modifiedmlir/lib/Transforms/LoopFusion.cpp
The file was modifiedmlir/lib/Transforms/Vectorize.cpp
The file was modifiedmlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
The file was modifiedmlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/CMakeLists.txt
The file was modifiedmlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
The file was modifiedmlir/lib/Dialect/LoopOps/LoopOps.cpp
The file was modifiedmlir/lib/Transforms/PipelineDataTransfer.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/EDSC/Builders.h
The file was modifiedmlir/lib/Analysis/Utils.cpp
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
The file was modifiedmlir/lib/Transforms/AffineLoopInvariantCodeMotion.cpp
The file was modifiedmlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp
The file was modifiedmlir/test/lib/Transforms/TestOpaqueLoc.cpp
The file was modifiedmlir/lib/Quantizer/Configurations/FxpMathConfig.cpp
The file was modifiedmlir/lib/Conversion/LoopsToGPU/LoopsToGPUPass.cpp
The file was modifiedmlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp
The file was modifiedmlir/lib/Transforms/Utils/FoldUtils.cpp
The file was modifiedmlir/test/lib/IR/TestMatchers.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/EDSC/Builders.h
The file was removedmlir/lib/Dialect/StandardOps/Ops.cpp
The file was removedmlir/include/mlir/Dialect/StandardOps/Ops.td
The file was modifiedmlir/test/lib/Transforms/TestLoopFusion.cpp
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.td
The file was modifiedmlir/lib/Dialect/VectorOps/VectorUtils.cpp
The file was modifiedmlir/test/lib/DeclarativeTransforms/TestVectorTransformPatterns.td
The file was modifiedmlir/lib/Dialect/AffineOps/AffineOps.cpp
The file was modifiedmlir/lib/Transforms/MemRefDataFlowOpt.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp
The file was addedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
The file was modifiedmlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp
The file was modifiedmlir/lib/Dialect/VectorOps/VectorTransforms.cpp
The file was modifiedmlir/lib/Conversion/LoopToStandard/ConvertLoopToStandard.cpp
The file was modifiedmlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/lib/Dialect/QuantOps/Transforms/ConvertConst.cpp
The file was addedmlir/include/mlir/Dialect/StandardOps/IR/Ops.h
The file was addedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
The file was modifiedmlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
The file was modifiedmlir/test/lib/Transforms/TestMemRefDependenceCheck.cpp
The file was modifiedmlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp
The file was modifiedmlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
The file was modifiedmlir/test/lib/Transforms/TestMemRefBoundCheck.cpp
The file was modifiedmlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
The file was modifiedmlir/lib/Transforms/LoopCoalescing.cpp
The file was modifiedmlir/test/lib/Transforms/TestConstantFold.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
The file was modifiedmlir/lib/Analysis/AffineAnalysis.cpp
The file was addedmlir/include/mlir/Dialect/StandardOps/IR/CMakeLists.txt
The file was modifiedmlir/lib/Transforms/Utils/Utils.cpp
The file was modifiedmlir/test/lib/Transforms/TestInlining.cpp
The file was modifiedmlir/lib/Analysis/NestedMatcher.cpp
The file was removedmlir/include/mlir/Dialect/StandardOps/Ops.h
The file was modifiedmlir/include/mlir/Dialect/StandardOps/CMakeLists.txt
The file was modifiedmlir/lib/Transforms/Utils/LoopFusionUtils.cpp
The file was modifiedmlir/include/mlir/InitAllDialects.h
The file was modifiedmlir/include/mlir/Transforms/Utils.h
The file was modifiedmlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/lib/Dialect/LoopOps/Transforms/ParallelLoopFusion.cpp
The file was modifiedmlir/lib/Dialect/VectorOps/VectorOps.cpp
The file was modifiedmlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
Commit e2ed1d14d6c2d11d1a5df23bd679bcb7e6cbf433 by francesco.petrogalli
[llvm][aarch64] SVE addressing modes.

Summary:
Added register + immediate and register + register addressing modes for the following intrinsics:

1. Masked load and stores:
     * Sign and zero extended load and truncated stores.
     * No extension or truncation.
2. Masked non-temporal load and store.

Reviewers: andwar, efriedma

Subscribers: cameron.mcinally, sdesmalen, tschuett, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74254
The file was addedllvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
The file was addedllvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
The file was addedllvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was addedllvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
Commit 34e3485560cbe8b0e843a1a9ef0cf796e6a4e237 by spatel
[VectorCombine] refactor cost calcs to reduce duplication; NFC

More cleanup is possible now, but we probably need to
resolve the TODO about the existing difference between
compares and binops.
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit 33bf1196475cbc9b84914c41308cf252764803ee by francesco.petrogalli
[llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE.

Summary: The patch covers both register/register and register/immediate addressing modes.

Reviewers: efriedma, andwar, sdesmalen

Reviewed By: sdesmalen

Subscribers: sdesmalen, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74581
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Commit 446b150065c331daa82a9f5436f4987e340e5d6f by rnk
[IR] Update BasicBlock::validateInstrOrdering comments, NFC

Pointed out by Jay Foad.
The file was modifiedllvm/lib/IR/BasicBlock.cpp
The file was modifiedllvm/include/llvm/IR/BasicBlock.h
Commit 8875ee18d72b1b395331c1b7217d2b91fb4dc4b7 by craig.topper
[X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix.

isPrefix was added to support the patches to align branches.
it relies on a switch over instruction names.

This moves those opcodes to a new format so the information is
tablegen and we can just check for a specific value in some bits
in TSFlags instead.

I've left the other function in place for now so that the
existing patches in phabricator will still work. I'll work with
the owner to get them migrated.
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/Target.cpp
The file was modifiedllvm/utils/TableGen/X86RecognizableInstr.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrFormats.td
The file was modifiedllvm/lib/Target/X86/X86InstrSystem.td
The file was modifiedllvm/lib/Target/X86/X86InstrTSX.td
The file was modifiedllvm/utils/TableGen/X86RecognizableInstr.h
Commit 1874dee5662603c9251228c71b66de72cec0c979 by francisvm
[macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat

This moves all the logic of converting LLVM Triples to
MachO::CPU_(SUB_)TYPE from the specific target (Target)AsmBackend to
more convenient functions in lib/BinaryFormat.

This also gets rid of the separate two X86AsmBackend classes.

The previous attempt was to add it to libObject, but that adds an
unnecessary dependency to libObject from all the targets.

Differential Revision: https://reviews.llvm.org/D74808
The file was modifiedllvm/lib/BinaryFormat/CMakeLists.txt
The file was modifiedllvm/include/llvm/BinaryFormat/MachO.h
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
The file was addedllvm/lib/BinaryFormat/MachO.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
Commit 0bb90628b5f7c170689d2d3f019af773772fc649 by hhb
Allow customized relative PYTHONHOME

Summary:
This change allows a hard coded relative PYTHONHOME setting. So that
python can easily be packaged together with lldb.

The change includes:
1. Extend LLDB_RELOCATABLE_PYTHON to all platforms. It defaults to ON
for platforms other than Windows, to keep the behavior compatible.
2. Allows to customize LLDB_PYTHON_HOME. But still defaults to
PYTHON_HOME.
3. LLDB_PYTHON_HOME can be a path relative to liblldb. If it is
relative, we will resolve it before send it to Py_DecodeLocale.

Subscribers: mgorny, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74727
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
The file was modifiedlldb/cmake/modules/LLDBConfig.cmake
The file was modifiedlldb/include/lldb/Host/Config.h.cmake
Commit 8fa776b8ed02f36e6bc072c6748725890dfadcbe by llvmgnsyncbot
[gn build] Port 1874dee5662
The file was modifiedllvm/utils/gn/secondary/llvm/lib/BinaryFormat/BUILD.gn
Commit e9c79a7aef19b14e68ed50eb9382856e9453c5a0 by spatel
[VectorCombine] refactor to reduce duplicated code; NFC

This should be the last step in the current cleanup.
Follow-ups should resolve the TODO about cost calc
and enable the more general case where we extract
different elements.
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit b72f1448ce42f4e38f0c2a33418089f2320ab8f3 by jay.foad
AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16

Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74987
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp