Changes

AMDGPU/GlobalISel: Fix constant bus violation with source modifiers

This looked through copies to find the source modifiers, which may
have been SGPR->VGPR copies added to avoid potential constant bus
violations. Re-insert a copy to a VGPR if this happens.

AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy

AMDGPU/GlobalISel: Legalize G_FPOW

There are few differences from the DAG handling. First, the DAG
handling uses a primitive selection pattern instead of custom
legalizing it. Because of this, this makes use of source modifiers
while the DAG does not.

Also instead of promoting f16, try to use the f16 log/exp. There's no
f16 fmul_legacy, so widen just for the multiply, although I'm not sure
that's the best solution.

AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC

We have patterns for s_pack* selection, but they assume the inputs are
a build_vector with 16-bit inputs, not a truncating build
vector. Since there's still outstanding work for how to handle
mismatched result and source element vector operations, and since I'm
trying a different packed vector strategy than SelectionDAG, just
manually select this for now.

[ARM] Correct Formatting. NFC

Also removed an unnecessary TODO that I don't believe is relevant for
the instruction in question.

AMDGPU/GlobalISel: Precommit xnor matching test

[ELF] Ignore the maximum of input section alignments for two cases

Follow-up for D74286.

Notations:

* alignExpr: the computed ALIGN value
* max_input_align: the maximum of input section alignments

This patch changes the following two cases to match GNU ld:

* When ALIGN is present, GNU ld sets output sh_addr to alignExpr, while lld use max(alignExpr, max_input_align)
* When addrExpr is specified but alignExpr is not, GNU ld sets output sh_addr to addrExpr, while lld uses `advance(0, max_input_align)`

Note, sh_addralign is still set to max(alignExpr, max_input_align).

lma-align.test is enhanced a bit to check we don't overalign sh_addr.

fixSectionAlignments() sets addrExpr but not alignExpr for the `!hasSectionsCommand` case.
This patch sets alignExpr as well so that max_input_align will be respected.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74736

[ELF] Warn changed output section address

When the output section address (addrExpr) is specified, GNU ld warns if
sh_addr is different. This patch implements the warning.

Note, LinkerScript::assignAddresses can be called more than once. We
need to record the changed section addresses, and only report the
warnings after the addresses are finalized.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74741

[lldb-vscode] Use libOption with tablegen to parse command line options.

This change will bring lldb-vscode in line with how several other llvm
tools process command line arguments and make it easier to add future
options.

Differential revision: https://reviews.llvm.org/D74798

[ELF] Shuffle .init_array/.fini_array with --shuffle-sections=

Useful for detecting static initialization order fiasco.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74887

[TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls.

Minor refactor/cleanup before we begin adding non-uniform support.

AMDGPU/GlobalISel: Fix xnor matching

We should try the generated matchers before the manual selection. This
means the patterns are now handling the common cases, but the manual
selection code is not yet dead. It's still handling the non-s32/s64
cases (like v2s16 and v2s32). Currently tablegen doesn't have a nice
way to have a single pattern that covers multiple types.

AMDGPU/GlobalISel: Commit test changes I forgot to squash

These should have been in ac7abe0ba9ae4c6a2248cc3ef4e4fe7e6d270105

GlobalISel: Fix narrowing of (G_ASHR i64:x, 32)

Reviewers: arsenm

Subscribers: jvesely, wdng, nhaehnle, rovka, hiraditya, volkan, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74950

[AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll

Add +fullfp16 to sve-vector-splat.ll so we can test folding of immediates into moves.

This attribute can go away later when SVE has a full set of fp16 patterns in place.

Differential Revision: https://reviews.llvm.org/D74965

[DSE,MSSA] Add debug counter.

Can be used like
-debug-counter=dse-memoryssa-skip=10,dse-memoryssa-counter-count=20

Reviewers: dmgreen, rnk, efriedma, bryant, asbirlea

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D72147

[AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls.

Summary:
This revision adds matchers that match calls to the gtest EXPECT and ASSERT
macros almost like function calls. The matchers are placed in separate files
(GtestMatchers...), because they are specific to the gtest library.

Reviewers: gribozavr2

Subscribers: mgorny, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74840

[VectorCombine] refactor matching code to reduce duplication; NFC

cmp/binop were already diverging even though they are largely
the same logic.

[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations

Summary:
Add intrinsics for the following operations:
- eor3, bcax
- bsl, bsl1n, bsl2n, nbsl

Fix MC tests for bsl instructions.

Reviewers: kmclaughlin, c-rhodes, sdesmalen, efriedma, rengolin

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74785

AMDGPU: Use default operand for VOP3P clamp

We don't use this, and matching from the def doesn't make much sense.

There are multiple tablegen bugs with default operand
handling. undef_tied_input should work to handle the vdst_in
correctly, but this breaks the operand register class constraint which
it should be able to infer.

[SystemZ]  Return scalarized costs for vector instructions on older archs.

A cost query for a vector instruction should return a cost even without
target vector support, and not trigger an assert.

VectorCombine does this with an input containing source code vectors.

Review: Ulrich Weigand

[gn build] Port 23444edf30b

[SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls

This changes the SimplifyLibCalls utility to accept an IRBuilderBase,
which allows us to pass through the IRBuilder used by InstCombine.
This will ensure that new instructions get added to the worklist.
The annotated test-case drops from 4 to 2 InstCombine iterations thanks
to this.

To achieve this, I'm adding an IRBuilderBase::OperandBundlesGuard,
which is basically the same as the existing InsertPointGuard and
FastMathFlagsGuard, but for operand bundles. Also add a
setDefaultOperandBundles() method so these can be set outside the
constructor.

Differential Revision: https://reviews.llvm.org/D74792

[X86] Fix SDLoc initialization

Fixes -Wparentheses warning, in this case indicating a genuine
bug.

[VectorUtils] Move ToVectorTy to VectorUtils.h (NFC).

ToVectorTy is defined and used in multiple places. Hoist it to
VectorUtils.h to avoid duplication and improve re-usability.

Reviewers: rengolin, hsaito, Ayal, gilr, fpetrogalli

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D74959

[DSE,MSSA] Dbg counters required assertions. Mark test accordingly.

[InstCombine] Use replaceOperand() in more places

Followup to D73919 with another batch of replacements of
setOperand() -> replaceOperand(), to make sure the old
operand gets DCEd right away.

Differential Revision: https://reviews.llvm.org/D74932

[Clang interpreter] Rename Block.{h,cpp} to InterpBlock.{h,cpp}

The Blocks runtime provide a header named Block.h.
It is generally preferable to avoid name collision with system headers
(reducing reliance on -isystem order, more friendly when navigating files in
an editor, etc).

Reviewed By: gribozavr2

Differential Revision: https://reviews.llvm.org/D74934

[BFI] Fix missed BFI updates in MachineSink.

Summary:
This prevents BFI queries on new blocks (from
MachineSinking::GetAllSortedSuccessors) and fixes a bunch of assert failures
under -check-bfi-unknown-block-queries=true.

Reviewers: davidxl

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74511

[InstCombine] Improve simplify demanded bits worklist management

This fixes a small mistake from D72944: The worklist add should
happen before assigning the new operand, not after.

In case an actual replacement happens, the old operand needs to
be added for DCE. If no actual replacement happens, then old/new
are the same, so it doesn't matter.

This drops one iteration from the annotated test case.

[llvm][CodeGen] DAG Combiner folds for vscale.

Summary:
This patch simplifies the DAGs generated when using the intrinsic `@llvm.vscale.*` as follows:

* Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
* Canonicalize (sub X, (vscale * C)) to (add X,  (vscale * -C)).
* Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)).
* Fold (shl (vscale * C0), C1) to (vscale * (C0 << C1)).

The test `sve-gep-ll` have been updated to reflect the folding introduced by this patch.

Reviewers: efriedma, sdesmalen, andwar, rengolin

Reviewed By: sdesmalen

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74782

[MLIR] Allow Loop dialect IfOp and ForOp to define values

This patch implements the RFCs proposed here:
https://llvm.discourse.group/t/rfc-modify-ifop-in-loop-dialect-to-yield-values/463
https://llvm.discourse.group/t/rfc-adding-operands-and-results-to-loop-for/459/19.

It introduces the following changes:
- All Loop Ops region, except for ReduceOp, terminate with a YieldOp.
- YieldOp can have variadice operands that is used to return values out of IfOp and ForOp regions.
- Change IfOp and ForOp syntax and representation to define values.
- Add unit-tests and update .td documentation.
- YieldOp is a terminator to loop.for/if/parallel
- YieldOp custom parser and printer

Lowering is not supported at the moment, and will be in a follow-up PR.

Thanks.

Reviewed By: bondhugula, nicolasvasilache, rriddle

Differential Revision: https://reviews.llvm.org/D74174

[XCOFF][AIX] Put undefined symbol name into StringTable when neccessary

Summary:
When we have a long name for the undefined symbol, we would hit this assertion:
Assertion failed: I != StringIndexMap.end() && "String is not in table!"
This patch addresses that.

Reviewed by: DiggerLin, daltenty

Differential Revision: https://reviews.llvm.org/D74924

[LoopVectorize][X86] Regenerate tests. NFCI.

Fix MSVC "not all control paths return a value" warning. NFCI.

AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR

G_SHUFFLE_VECTOR is legal since it theoretically may help match op_sel
for VOP3P instructions. Expand it in some other way in case it doesn't
fold into the use instructions.

AMDGPU/GlobalISel: Select VOP3P instructions

This only handles the basic cases. More work is needed to make better
use of op_sel.

AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2

I'm slighly worried about the generated checks, since they won't catch
incorrect modifiers being added at the end of the line.

AMDGPU: Move dot intrinsic patterns to instruction def

I tried to use some of the new tablegen features to avoid creating
different operand list permutations, but I still don't see a way to
programmatically build a source pattern dag.

Also add GlobalISel tests, which now all import successfully.

Some of the fneg fold tests are incorrect, which need to be fixed in a
future commit

[lldb/cmake] Enable more verbose find_package output.

Summary:
The purpose of this patch is to make identifying missing dependencies clearer to the user.
`find_package` will report if a package is not found, that output, combined with the exiting
status message, is clearer than not having the additional verbosity.

If the SWIG dependency is required {LLDB_ENABLE_PYTHON, LLDB_ENABLE_LUA}
and SWIG is not available, fail the configuration step.  Terminate the
configure early rather than later with a clear error message.

We could possibly modify:
`llvm-project/lldb/cmake/modules/FindPythonInterpAndLibs.cmake`
However, the patch here seems clear in my opinion.

Reviewers: aadsm, hhb, JDevlieghere

Reviewed By: JDevlieghere

Subscribers: labath, jrm, mgorny, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74917

AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max

The legalizer helper functions are unusably awkward to perform the 3-5
part legalization. This needs to be widened, scalarized, lowered, and
we should avoid creating vector extends and truncates. Manually do all
of this and expand.

[ARM] Change ARMAttributeParser::Parse to use support::endianness and simplify

[libc++] Do not set the `availability=XXX` feature when not testing against a system libc++

Otherwise, the `availability=XXX` lit feature is set even when we're
testing trunk and _LIBCPP_DISABLE_AVAILABILITY is defined, which causes
tests that check for availability markup to be enabled and unexpectedly
pass.

[AArch64][SVE] Add backend support for splats of immediates

This patch adds backend support for splats of both Int and FP immediates.

Differential Revision: https://reviews.llvm.org/D74856

[CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

By default the RISC-V target doesn't have the atomics standard extension
enabled. The first RUN line in `clang/test/CodeGen/atomic_ops.c` didn't
specify a target triple, which meant that on RISC-V Linux hosts it would
target RISC-V, but because it used clang cc1 we didn't get the toolchain
driver functionality to automatically turn on the extensions implied by
the target triple (riscv64-linux includes atomics). This would cause the
test to fail on RISC-V hosts.

This patch changes the test to have RUN lines for two explicit targets,
one with native atomics and one without. To work around FileCheck
limitations and more accurately match the output, some tests now have
separate prefixes for the two cases.

Reviewers: jyknight, eli.friedman, lenary, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D74847

[mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V.

Differential Revision: https://reviews.llvm.org/D74874

[MLIR] Remove constexpr from LoopOps.td

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D74978

[Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q if possible

When each byte in b&m is non-zero, this conversion Q->V->Q is a no-op.

Move StandardOps/Ops.h to StandardOps/IR/Ops.h

Summary:
NFC - Moved StandardOps/Ops.h to a StandardOps/IR dir to better match surrounding
directories. This is to match other dialects, and prepare for moving StandardOps
related transforms in out for Transforms and into StandardOps/Transforms.

Differential Revision: https://reviews.llvm.org/D74940

[llvm][aarch64] SVE addressing modes.

Summary:
Added register + immediate and register + register addressing modes for the following intrinsics:

1. Masked load and stores:
     * Sign and zero extended load and truncated stores.
     * No extension or truncation.
2. Masked non-temporal load and store.

Reviewers: andwar, efriedma

Subscribers: cameron.mcinally, sdesmalen, tschuett, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74254

[VectorCombine] refactor cost calcs to reduce duplication; NFC

More cleanup is possible now, but we probably need to
resolve the TODO about the existing difference between
compares and binops.

[llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE.

Summary: The patch covers both register/register and register/immediate addressing modes.

Reviewers: efriedma, andwar, sdesmalen

Reviewed By: sdesmalen

Subscribers: sdesmalen, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74581

[IR] Update BasicBlock::validateInstrOrdering comments, NFC

Pointed out by Jay Foad.

[X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix.

isPrefix was added to support the patches to align branches.
it relies on a switch over instruction names.

This moves those opcodes to a new format so the information is
tablegen and we can just check for a specific value in some bits
in TSFlags instead.

I've left the other function in place for now so that the
existing patches in phabricator will still work. I'll work with
the owner to get them migrated.

[macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat

This moves all the logic of converting LLVM Triples to
MachO::CPU_(SUB_)TYPE from the specific target (Target)AsmBackend to
more convenient functions in lib/BinaryFormat.

This also gets rid of the separate two X86AsmBackend classes.

The previous attempt was to add it to libObject, but that adds an
unnecessary dependency to libObject from all the targets.

Differential Revision: https://reviews.llvm.org/D74808

Allow customized relative PYTHONHOME

Summary:
This change allows a hard coded relative PYTHONHOME setting. So that
python can easily be packaged together with lldb.

The change includes:
1. Extend LLDB_RELOCATABLE_PYTHON to all platforms. It defaults to ON
for platforms other than Windows, to keep the behavior compatible.
2. Allows to customize LLDB_PYTHON_HOME. But still defaults to
PYTHON_HOME.
3. LLDB_PYTHON_HOME can be a path relative to liblldb. If it is
relative, we will resolve it before send it to Py_DecodeLocale.

Subscribers: mgorny, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D74727

[gn build] Port 1874dee5662

[VectorCombine] refactor to reduce duplicated code; NFC

This should be the last step in the current cleanup.
Follow-ups should resolve the TODO about cost calc
and enable the more general case where we extract
different elements.

AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16

Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74987