Changes

[Hexagon] Add support for Hexagon/HVX v67 ISA

AMDGPU: Partially merge indirect register write handling
a785209bc2fb switched to using a pseudos instead of manually tying 
operands on the regular instruction. The VGPR indexing mode path should
have the same problems that change attempted to avoid, so these should
use the same strategy.
Use a single pseudo for the VGPR indexing mode and movreld paths, and 
expand it based on the subtarget later. These have essentially the same
constraints, reading the index from m0.
Switch from using an offset to the subregister index directly, instead 
of computing an offset and re-adding it back. Also add missing pseudos 
for existing register class sizes.

AMDGPU: Prepare to use scalar register indexing
Define pseudos mirroring the the VGPR indexing ones, and adjust the 
operands in the s_movrel* instructions to avoid the result def.