Started 1 mo 4 days ago
Took 1 hr 20 min on labmaster2

Success Build #9688 (Feb 24, 2020 12:04:10 PM)


Git (git http://labmaster3.local/git/llvm-project.git)

  1. Revert "[macho][NFC] Extract all CPU_(SUB_)TYPE logic to libObject" (detail)
  2. [PowerPC][NFC] Cleanup some of the Darwin mentions in the README.txt. (detail)
  3. [x86] allow peeking through an extract_subvector to find a splatted operand (detail)
  4. [libc] Add Initial Support for Signals (detail)
  5. Fix some typos in the MLIR documentation. (detail)
  6. [ORC][examples] Fix ThinLtoJIT example after changes in 85fb997659b. (detail)
  7. [ORC] Add a convenience method for setting the ExecutionSession to LLJITBuilder. (detail)
  8. [X86] Fix NSW/NUW typo in avg test (PR44973) (detail)
  9. [clang-format] Merge name and colon into a single token for C# named arguments (detail)
  10. libclang: Make shared object symbol exporting by default (detail)
  11. [AIX] Pack BasicBlockBits (detail)
  12. [clang][doxygen] Fix false -Wdocumentation warning for tag typedefs (detail)
  13. [GISel][KnownBits] Give up on PHI analysis as soon as we don't know anything (detail)
  14. [cxx_status] Update -std= instructions for C++20. (detail)
  15. [llvm][build] Fix shared lib builds. [NFC] (detail)
  16. Revert "[NFCI][DebugInfo]: Corrected a Typo." (detail)
  17. [ConstantFold] add/move tests for FP with undef operand; NFC (detail)
  18. Revert "[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations" (detail)
  19. Revert "libclang: Add static build support for Windows" and (detail)
  20. [X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT (detail)
  21. Revert 714265dabb606bfef2f85694234f152edbfa91ac "[X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT" (detail)
  22. Recommit "[X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT"" (detail)
  23. [AIX] Improve 32/64-bit build configuration (detail)
  24. [ASTImporter] Add linkage check to ASTNodeImporter::hasSameVisibilityContext and rename to hasSameVisibilityContextAndLinkage (detail)
  25. [Driver] Escape the program path for -frecord-command-line (detail)
  26. [SVE] Add support for lowering GEPs involving scalable vectors. (detail)
  27. [SCCP] Do not mark unknown loads as overdefined. (detail)
  28. [mlir] [VectorOps] Multi-dim reductions for lowering vector.contract (detail)
  29. [mlir] Use LLJIT::getMainJITDylib instead of hardcoding '<main>' (detail)
  30. [lldb/Plugin] Don't mark ProcessNetBSD as a plugin (detail)
  31. Revert "[Driver] Escape the program path for -frecord-command-line" (detail)
  32. [mlir][Parser] Update DenseElementsAttr to print in hex when the number of elements is over a certain threshold. (detail)
  33. [lldb/Test] Remove stale README in test/API (detail)
  34. [libc++] Explain XFAILs with std::uncaught_exceptions test (detail)
  35. [X86] Custom legalize v1i1 add/sub/mul to xor/xor/and with avx512. (detail)
  36. [X86] Fix a couple copy mistakes in v4i1 or/and/xor isel patterns. (detail)
  37. [X86] Custom legalize v1i1 UADDSAT/USUBSAT/SADDSAT/UADDSAT to match v2i1/v4i1/v8i1 etc. (detail)
  38. [X86] Expand vselect of v1i1 under avx512. (detail)
  39. [X86] Add CMOV_VK1 pseudo so we don't crash on v1i1 ISD::SELECT (detail)
  40. [libc++][regex] Validate backreferences in the constructor. (detail)
  41. [libunwind][CMake] Treat S files as C to work around CMake bug. (detail)
  42. Filter callbr insts from critical edge splitting (detail)
  43. [Dominators] Use Instruction::comesBefore for block-local queries, NFC (detail)
  44. [XCore] Add instruction pattern for bitrev (detail)
  45. [OpenMP][NFC] Remove leftover debug messages (detail)
  46. [mlir] Use getOperation()->setAttr when generating attribute set (detail)
  47. Split _LIBCPP_STRING_EXTERN_TEMPLATE_LIST up into a V1 and UNSTABLE version. (detail)
  48. [X86] Add CMOV_VR64 pseudo instruction for MMX. Remove mmx handling from combineSelect. (detail)
  49. libclc: Use acos implementation from amd_builtins (detail)
  50. [X86] Remove unnecessary isNullConstant in LowerSelect. NFC (detail)
  51. [WebAssembly] Remove unneeded getWasmKindForNamedSection function (detail)
  52. [X86] Autogenerate complete checks. NFC (detail)
  53. [X86] Make combineCMov not create unsupported FCMOVs when f32/f64 are using X87. (detail)
  54. [X86] Don't bother avoiding illegal FCMOVs if we don't have the cmov subtarget feature. (detail)
  55. [clangd] Fix the incomplete template specialization in findTarget. (detail)
  56. [lldb][NFC] Split up ClangASTSource::FindExternalVisibleDecls (detail)
  57. [clangd] Allow renaming class templates in cross-file rename. (detail)
  58. Make unittests include path relative (detail)
  59. [NFC][mlir] Adding more operators to EDSC TemplatedIndexedValue (detail)
  60. test/CodeGen/AMDGPU: Add a test case that shows a miscompilation (detail)
  61. [NFC] Corrected a minor typo in a comment (detail)
  62. Detect and disable openmp tests that require multiple hardware processor to run (detail)
  63. [ConstantFold] fold fsub -0.0, undef to undef rather than NaN (detail)
  64. [DependenceAnalysis] Memory dependence analysis internal caching mechanism is broken in presence of TBAA (PR42733). (detail)
  65. [Hexagon] Introduce noop intrinsic to cast between vector predicate types (detail)
  66. [mlir] Add a signedness semantics bit to IntegerType (detail)
  67. [TargetLowering] SimplifyDemandedBits - use getValidShiftAmountConstant helper. (detail)
  68. [X86] Regenerate hi reg tests (detail)
  69. [Error/unittests] Add a FailedWithMessage gtest matcher (detail)
  70. [PowerPC][NFC] Remove Darwin specific logic in frame finalization. (detail)
  71. [AST][NFC] Update outdated comments in ASTStructuralEquivalence.cpp (detail)
  72. [PowerPC][NFC] Add a test for vrsave usage iinline asm. (detail)
  73. [lldb/DWARF] Add support for type units in dwp files (detail)
  74. Remove unused functions in llvm-ml (detail)
  75. [mlir] Silence error: call to constructor of 'llvm::APInt' is ambiguous (detail)
  76. AMDGPU/GlobalISel: Fix constant bus violation with source modifiers (detail)
  77. AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy (detail)
  78. AMDGPU/GlobalISel: Legalize G_FPOW (detail)
  79. AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC (detail)
  80. [ARM] Correct Formatting. NFC (detail)
  81. AMDGPU/GlobalISel: Precommit xnor matching test (detail)
  82. [ELF] Ignore the maximum of input section alignments for two cases (detail)
  83. [ELF] Warn changed output section address (detail)
  84. [lldb-vscode] Use libOption with tablegen to parse command line options. (detail)
  85. [ELF] Shuffle .init_array/.fini_array with --shuffle-sections= (detail)
  86. [TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls. (detail)
  87. AMDGPU/GlobalISel: Fix xnor matching (detail)
  88. AMDGPU/GlobalISel: Commit test changes I forgot to squash (detail)
  89. GlobalISel: Fix narrowing of (G_ASHR i64:x, 32) (detail)
  90. [AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll (detail)
  91. [DSE,MSSA] Add debug counter. (detail)
  92. [AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls. (detail)
  93. [VectorCombine] refactor matching code to reduce duplication; NFC (detail)
  94. [AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations (detail)
  95. AMDGPU: Use default operand for VOP3P clamp (detail)
  96. [SystemZ]  Return scalarized costs for vector instructions on older archs. (detail)
  97. [gn build] Port 23444edf30b (detail)
  98. [SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls (detail)
  99. [X86] Fix SDLoc initialization (detail)
  100. [VectorUtils] Move ToVectorTy to VectorUtils.h (NFC). (detail)
  101. [DSE,MSSA] Dbg counters required assertions. Mark test accordingly. (detail)
  102. [InstCombine] Use replaceOperand() in more places (detail)
  103. [Clang interpreter] Rename Block.{h,cpp} to InterpBlock.{h,cpp} (detail)
  104. [BFI] Fix missed BFI updates in MachineSink. (detail)
  105. [InstCombine] Improve simplify demanded bits worklist management (detail)
  106. [llvm][CodeGen] DAG Combiner folds for vscale. (detail)
  107. [MLIR] Allow Loop dialect IfOp and ForOp to define values (detail)
  108. [XCOFF][AIX] Put undefined symbol name into StringTable when neccessary (detail)
  109. [LoopVectorize][X86] Regenerate tests. NFCI. (detail)
  110. Fix MSVC "not all control paths return a value" warning. NFCI. (detail)
  111. AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR (detail)
  112. AMDGPU/GlobalISel: Select VOP3P instructions (detail)
  113. AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2 (detail)
  114. AMDGPU: Move dot intrinsic patterns to instruction def (detail)
  115. [lldb/cmake] Enable more verbose find_package output. (detail)
  116. AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max (detail)
  117. [ARM] Change ARMAttributeParser::Parse to use support::endianness and simplify (detail)
  118. [libc++] Do not set the `availability=XXX` feature when not testing against a system libc++ (detail)
  119. [AArch64][SVE] Add backend support for splats of immediates (detail)
  120. [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V (detail)
  121. [mlir][spirv] Add lowering for load/store zero-rank memref from std to SPIR-V. (detail)
  122. [MLIR] Remove constexpr from (detail)
  123. [Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q if possible (detail)
  124. Move StandardOps/Ops.h to StandardOps/IR/Ops.h (detail)
  125. [llvm][aarch64] SVE addressing modes. (detail)
  126. [VectorCombine] refactor cost calcs to reduce duplication; NFC (detail)
  127. [llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics for SVE. (detail)
  128. [IR] Update BasicBlock::validateInstrOrdering comments, NFC (detail)
  129. [X86] Add a new format type for instructions that represent named prefix bytes like data16 and rep. Use it to make a simpler version of isPrefix. (detail)
  130. [macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat (detail)
  131. Allow customized relative PYTHONHOME (detail)
  132. [gn build] Port 1874dee5662 (detail)
  133. [VectorCombine] refactor to reduce duplicated code; NFC (detail)
  134. AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16 (detail)
  135. [AArch64][SVE] Add support for DestructiveBinary and DestructiveBinaryComm DestructiveInstTypes (detail)
  136. [llvm-objcopy][MachO] Change the storage of sections (detail)
  137. [lldb/test] Move `platform process list` tests to its own directory (NFC) (detail)
  138. [lldb/Plugins] Add ability to fetch crash information on crashed processes (detail)
  139. [AArch64][SVE] Fix -Wimplicit-fallthrough after D73711 (detail)
  140. clang/Modules: Finish renaming CompilerInstance::ModuleManager, NFC. (detail)
  141. [SelectionDAG] remove unused isFast() helper function; NFC (detail)
  142. [AArch64][SVE] Fix -DBUILD_SHARED_LIBS=on builds after -D74808/1874dee5662603c9251228c71b66de72cec0c979 (detail)
  143. [AArch64] Delete an unneeded dependency on Object after 1874dee5662603c9251228c71b66de72cec0c979 (detail)
  144. [Hexagon] Define __ELF__ by default. (detail)
  145. [CloneFunction] Update loop headers after cloning all blocks in loop. (detail)
  146. [Attributor][FIX] Undo 16188f9 until SCC iterator bug is fixed (detail)
  147. [GISel][KnownBits] Add a cache mechanism to speed compile time (detail)
  148. [Attributor][FIX] Disable a test to unblock the builders (detail)
  149. [Target] Remove libObject dependency in lib/Target (detail)
  150. Revert "Allow customized relative PYTHONHOME" (detail)
  151. [Analysis][Docs] Parents of loops documentation. (detail)
  152. [mlir][DeclarativeParser] Add support for the TypesMatchWith trait. (detail)
  153. [mlir][DeclarativeParser] Add basic support for optional groups in the assembly format. (detail)
  154. [mlir][DeclarativeParser] Add an 'attr-dict-with-keyword' directive (detail)
  155. [mlir] Add a utility iterator range that repeats a given value `n` times. (detail)
  156. [mlir][ODS] Add support for specifying the successors of an operation. (detail)
  157. [mlir][DeclarativeParser] Add support for formatting the successors of an operation. (detail)
  158. [mlir][Tutorial] Add a section to Toy Ch.2 detailing the custom assembly format. (detail)
  159. [llvm-objdump] Print method name from debug info in disassembly output. (detail)
  160. [MC][ELF] Error for sh_type, sh_flags or sh_entsize change (detail)
  161. [lldb/test] Tweak libcxx string test on Apple+ARM devices (detail)
  162. Revert "[AMDGPU] Don’t marke the .note section as ALLOC" (detail)
  163. [mlir][DeclarativeParser][NFC] Use explicit type names in TypeSwitch to (detail)
  164. [Driver] Escape the program path for -frecord-command-line (detail)
  165. AMDGPU/GlobalISel: Remove dead code (detail)
  166. Allow customized relative PYTHONHOME (Attemp 1) (detail)
  167. [llvm-objdump][test] Fix source-interleave-function-from-debug.test on Windows after D74507 (detail)
  168. [WebAssembly] Fix a non-determinism problem in FixIrreducibleControlFlow (detail)
  169. Flags for displaying only hot nodes in CFGPrinter graph (detail)
  170. [lldb][test] Fix sh_type of .debug_cu_index and .debug_tu_index (detail)
  171. Remove unused variable (detail)
  172. [X86] Teach combineCVTPH2PS to shrink v8i16 loads when the output type is v4f32. Remove extra isel patterns. (detail)
  173. [lldb][test] Fix sh_flags and sh_entsize of .debug_str.dwo (detail)
  174. [libc] Lay out framework for fuzzing libc functions. (detail)
  175. [GISel][KnownBits] Suppress unused warning on the dump method (detail)
  176. [Preprocessor][test] Move AArch64 tests from init.c to init-aarch.c (detail)
  177. [Preprocessor][test] Fix __VERSION__ in init-aarch64.c (detail)
  178. [Frontend] Replace CC1 option -mcode-model with -mcmodel= (detail)
  179. [AArch64] Predefine __AARCH64_CMODEL_*__ as GCC does (detail)
  180. [Preprocessor][X86] Fix __code_model_*__ predefine macros (detail)
  181. Update (detail)
  182. Update (detail)
  183. [VE][fix] missing include (detail)
  184. [yaml2obj] - Automatically assign sh_addr for allocatable sections. (detail)
  185. [lldb][test] - Update basic-elf.yaml to fix build bot. (detail)
  186. [NFC] Remove some GCC warning from c9e93c84f61400d1aac7d195a0578e80bc48c69a (detail)
  187. [libcxx] [test] Suppress MSVC++ warning 4640 under /Zc:threadSafeInit- (detail)
  188. Add a llvm::shuffle and use it in lld (detail)
  189. [Sema] Fix pointer-to-int-cast diagnostic for _Bool (detail)
  190. [ORC] Add errors for missing and extraneous symbol definitions. (detail)
  191. [ORC] Update LLJIT to automatically run specially named initializer functions. (detail)
  192. [X86] Use movlps for i64 atomic stores on 32-targets with sse1. (detail)
  193. [X86] Teach EltsFromConsecutiveLoads that it's ok to form a v4f32 VZEXT_LOAD with a 64 bit memory size on SSE1 targets. (detail)
  194. [X86] Add AddToWorklist(N) after calls to SimplifyDemandedBits/SimplifyDemandedVectorElts that are called on an operand of N. (detail)
  195. [X86] Add sse2 command lines to sse-intrinsics-fast-isel.ll. (detail)
  196. [NFC] Test commit access. Drop trivial braces. (detail)
  197. [NFC] fix test nan value (detail)
  198. [clangd] Debounce rebuilds responsively to rebuild times. (detail)
  199. [clangd] Reapply b60896fad926 Fall back to selecting token-before-cursor if token-after-cursor fails. (detail)
  200. Revert "[clangd] Reapply b60896fad926 Fall back to selecting token-before-cursor if token-after-cursor fails." (detail)
  201. [DSE] Track overlapping stores. (detail)
  202. [SDAG] fold fsub -0.0, undef to undef rather than NaN (detail)
  203. [X86] Regenerate some tests to show FMA4 comments. NFC (detail)
  204. Recommit "[PatternMatch] Match XOR variant of unsigned-add overflow check." (detail)
  205. [AArch64] Update new test. (detail)
  206. [clangd] Reapply b60896fad926 Fall back to selecting token-before-cursor if token-after-cursor fails. (detail)
  207. Updating a comment to clarify that SkipUntil handles balanced delimiters. (detail)
  208. [clangd] Try to fix buildbots - copy elision not happening here? (detail)
  209. [SystemZ]  Support the kernel back chain. (detail)
  210. [X86] Use FIST for i64 atomic stores on 32-bit targets without SSE. (detail)
  211. [X86] Enable the use of movlps for i64 atomic load on 32-bit targets with sse1. (detail)
  212. [X86] Remove most X86 specific subclasses of MemSDNode. Just use a MemIntrinsicSDNode as we usually do. (detail)
  213. [SelectionDAG] Remove SelectionDAG::getTargetMemSDNode now that its not used. (detail)
  214. IR printing for single function with the new pass manager. (detail)
  215. [NFC][PowerPC] Refactor the tryAndWithMask() (detail)
  216. [Driver][X86] Add helptext for malign-branch*, mbranches-within-32B-boundaries (detail)
  217. [libc] Add a README to the sub-directories under the utils directory. (detail)
  218. [SelectionDAG] Remove ISD::LIFETIME_START/LIFETIME_END from assert in getMemIntrinsicNode. (detail)
  219. [X86] Use custom isel for gather/scatter instructions. (detail)
  220. [X86] When creating X86ISD::MGATHER nodes from AVX2 gather intrinsics, cast the mask to integer type. (detail)
  221. [JITLink] Add a MachO x86-64 GOT and Stub bypass optimization. (detail)
  222. [lldb] Remove all the 'current_id'  logging counters from the lookup code. (detail)
  223. [ARM][MVE] Combine more extending masked loads (detail)
  224. [lldb/DWARF] Don't index dwp file multiple times (detail)
  225. [lldb/test] simplify basic-elf.yaml (detail)
  226. [lldb] Disable auto fix-its when evaluating expressions in the test suite (detail)
  227. [MC] Widen the functional unit type from 32 to 64 bits. (detail)
  228. Use new FailedWithMessage matcher in DWARFDebugLineTest.cpp (detail)
  229. [profile] Don't dump counters when forking and don't reset when calling exec** functions (detail)
  230. [Intrinsic] Add fixed point saturating division intrinsics. (detail)
  231. Add a basic tiling pass for parallel loops (detail)
  232. Silence compiler warnings (detail)
  233. [AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions (detail)
  234. [ORC] Remove spammy debug print (detail)
  235. Use temporary directory for tests in D74346 (detail)
  236. [CostModel][X86] Try to check against common prefixes before using target-specific cpu checks (detail)
  237. [ARM] FP16 bitcast test. NFC (detail)
  238. [ARM,MVE] Remove 64-bit variants of vbrsrq* intrinsics (detail)
  239. Fix TryParsePtrOperatorSeq. (detail)
  240. [RDA][ARM][LowOverheadLoops] Iteration count IT blocks (detail)
  241. [AArch64][SVE] Add the SVE dupq_lane intrinsic (detail)
  242. [MIR][ARM] MachineOperand comments (detail)
  243. [CostModel][X86] We don't need a scale factor for SLM extract costs (detail)
  244. add release notes for ffp-model and ffp-exception-behavior (detail)
  245. [AIX][Frontend] C++ ABI customizations for AIX boilerplate (detail)
  246. [OpenMP] Refactor the analysis in checkMapClauseBaseExpression using StmtVisitor class. (detail)
  247. [libc++] Implementation of C++20's P1135R6 for libcxx (detail)
  248. [libc++] Adapt a few things around the implementation of P1135R6 (detail)
  249. [libc++] Mark the C++03 version of std::function as deprecated (detail)
  250. [lldb/DWARF] Fix dwp search path in the separate-debug-file case (detail)
  251. [PowerPC][AIX] Spill/restore the callee-saved condition register bits. (detail)
  252. [X86] getTargetShuffleInputs - check that the source inputs are all the right size. (detail)
  253. [gn build] (manually) merge 54fa9ecd308 (detail)
  254. [libc++] Fix CI and Linux failures after landing D68480 (detail)
  255. [gn build] remove -std=c++11 in libcxx build pending discussion in 80e73f2 review thread (detail)
  256. Revert "Rework go bindings so that validation works fine" (detail)
  257. [NFC] Fix typo in error message (detail)
  258. [libc++] Drop redundant check for -std=c++14 (detail)
  259. [ReleaseNotes] Mention the `vector-function-abi-variant` attribute. (detail)
  260. [CMake] Default to static linking for subprojects. (detail)
  261. [XCOFF][AIX] Fix incorrect alignment for function descriptor csect (detail)
  262. [AVR] Use correct register class for mul instructions (detail)
  263. [AVR] Don't assert on an undefined operand (detail)
  264. [X86] combineX86ShuffleChain - select X86ISD::FAND/ISD::AND based on MaskVT (detail)
  265. [AVR] Disassemble register operands (detail)
  266. [bindings/go] Add RemoveFromParentAsInstruction (detail)
  267. [MachO] Add cpu(sub)type tests and improve error handling (detail)
  268. [SelectionDAG] Merge constant SDNode arithmetic into foldConstantArithmetic (detail)
  269. [LLVM-C] Add bindings for addCoroutinePassesToExtensionPoints (detail)
  270. [mlir][spirv] NFC: Move test passes to test/lib (detail)
  271. [libc++] Give headers that require C++14 a cplusplus14 requires in the modulemap (detail)
  272. [AMDGPU] use llvm_unreachable instead of default for rp set (detail)
  273. [X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation (detail)

Started by an SCM change

This run spent:

  • 9.2 sec waiting;
  • 1 hr 20 min build duration;
  • 1 hr 20 min total from scheduled to completion.
Revision: 0d59095493ec8d189240307396e28105fc75ac37
  • refs/remotes/origin/master
Revision: e630ecf2f321b7a37e915a51088983bb109f0d6a
  • refs/remotes/origin/master
Revision: 727328433ad61b8c7acdd4d63e73241303a6beb7
  • refs/remotes/origin/master
Cobol Warnings: 0 warnings.
  • No warnings since build 534.
  • New zero warnings highscore: no warnings for 635 days!
Test Result (no failures)