Changes from Git (git http://labmaster3.local/git/llvm-project.git)


  1. GlobalISel: Change representation of shuffle masks (details)
  2. GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR (details)
  3. Fix crash on switch conditions of non-integer types in templates (details)
  4. [ORC] Refactor definition-generation, add a generator for static (details)
  5. GlobalISel: Implement lower for G_SHUFFLE_VECTOR (details)
  6. [lld][test] Update test to print ELF note description data (details)
  7. [ARM] Fix encoding of APSR in CLRM instruction (details)
  8. [ARM] Fix detection of duplicates when parsing reg list operands (details)
Commit 5af9cf042f21d6b044f8925b581a8f089d739bc5 by Matthew.Arsenault
GlobalISel: Change representation of shuffle masks
Currently shufflemasks get emitted as any other constant, and you end up
with a bunch of virtual registers of G_CONSTANT with a G_BUILD_VECTOR.
The AArch64 selector then asserts on anything that doesn't fit this
pattern. This isn't an ideal representation, and should avoid
legalization and have fewer opportunities for a representational error.
Rather than invent a new shuffle mask operand type, similar to what
ShuffleVectorSDNode does, just track the original IR Constant mask
operand. I don't completely like the idea of adding another link to the
IR, but MIR is already quite dependent on IR constants already, and this
will allow sharing the shuffle mask utility functions with the IR.
llvm-svn: 368704
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was addedllvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid2.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.cpp
The file was addedllvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid0.mir
The file was modifiedllvm/include/llvm/Target/
The file was addedllvm/test/CodeGen/MIR/AArch64/parse-shufflemask.mir
The file was addedllvm/test/MachineVerifier/test_g_shuffle_vector.mir
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was addedllvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid3.mir
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.h
The file was modifiedllvm/include/llvm/CodeGen/MachineInstrBuilder.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was addedllvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid1.mir
The file was modifiedllvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineOperand.h
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
Commit 0a04a062500e2c6d5b92b59c545db3f45e9daffe by Matthew.Arsenault
GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR
llvm-svn: 368705
The file was modifiedllvm/test/MachineVerifier/test_g_shuffle_vector.mir
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/test/CodeGen/MIR/AArch64/parse-shufflemask.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
Commit 76945821b9cad3baebad5c36ae00ab173f8529c6 by elizabeth.andrews
Fix crash on switch conditions of non-integer types in templates
Clang currently crashes for switch statements inside a template when the
condition is a non-integer field. The crash is due to incorrect
type-dependency of field. Type-dependency of member expressions is
currently set based on the containing class. This patch changes this for
'members of the current instantiation' to set the type dependency based
on the member's type instead.
A few lit tests started to fail once I applied this patch because errors
are now diagnosed earlier (does not wait till instantiation). I've
modified these tests in this patch as well.
Patch fixes PR#40982
Differential Revision:
llvm-svn: 368706
The file was addedclang/test/SemaTemplate/non-integral-switch-cond.cpp
The file was modifiedclang/test/SemaTemplate/dependent-names.cpp
The file was modifiedclang/lib/AST/Expr.cpp
The file was modifiedclang/test/SemaTemplate/enum-argument.cpp
The file was modifiedclang/test/SemaTemplate/member-access-expr.cpp
The file was modifiedclang/lib/Sema/SemaChecking.cpp
Commit 52a34a78d9aff1bb5e66e7c32490229ea177e075 by Lang Hames
[ORC] Refactor definition-generation, add a generator for static
This patch replaces the JITDylib::DefinitionGenerator typedef with a
class of the same name, and adds support for attaching a sequence of
DefinitionGeneration objects to a JITDylib.
This patch also adds a new definition generator,
StaticLibraryDefinitionGenerator, that can be used to add symbols fom a
static library to a JITDylib. An object from the static library will be
added (via a supplied ObjectLayer reference) whenever a symbol from that
object is referenced.
To enable testing, lli is updated to add support for the --extra-archive
option when running in -jit-kind=orc-lazy mode.
llvm-svn: 368707
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/ExecutionUtils.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
The file was addedllvm/test/ExecutionEngine/OrcLazy/static-library-support.ll
The file was modifiedllvm/tools/lli/lli.cpp
The file was modifiedllvm/tools/llvm-jitlink/llvm-jitlink.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/Core.h
Commit 690645bda08835abd0263f4e81113a31b3a9c52b by Matthew.Arsenault
GlobalISel: Implement lower for G_SHUFFLE_VECTOR
llvm-svn: 368709
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 7859641626f8125c0b8e0c2823745edfbe0aa27f by rupprecht
[lld][test] Update test to print ELF note description data
llvm-svn: 368710
The file was modifiedlld/test/ELF/partition-notes.s
Commit f990e4a4c7bcc3c3dec6ee8ffac39cc0a27e521a by momchil.velikov
[ARM] Fix encoding of APSR in CLRM instruction
The APSR is encoded by setting bit 15 in the register list of the CLRM
instruction (cf.
Differential Revision:
llvm-svn: 368711
The file was modifiedllvm/test/MC/ARM/clrm-asm.s
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
The file was modifiedllvm/lib/Target/ARM/
Commit 114c37e72a5f01f49761b42b3ff45334ed863a81 by momchil.velikov
[ARM] Fix detection of duplicates when parsing reg list operands
Differential Revision:
llvm-svn: 368712
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was addedllvm/test/MC/ARM/register-list-dup.s