Changes

[AArch64][GlobalISel] Fix manual selection for v4s16 and v8s8 G_DUP

The manual G_DUP selection code would produce DUPv16i8 for v8s8s and DUPv8i16
for v4s16.

This adds the missing cases to the manual selection code, and makes it return
false when there is an unexpected size.

Update select-dup.mir to reflect the change.

Differential Revision: https://reviews.llvm.org/D97240

Remove a workaround for MSVC 2013, now that MSVC 2017 is the minimum.

In MSVC 2013, 'alignas(integer-template-arg)' didn't compile; verified
on godbolt that this now works properly.

[llvm-objcopy] If input=output, preserve umask bits, otherwise drop S_ISUID/S_ISGID bits

This makes the behavior similar to cp

```
chmod u+s,g+s,o+x a
sudo llvm-strip a -o b
// With this patch, b drops set-user-ID and set-group-ID bits.
// sudo cp a b => b does not have set-user-ID or set-group-ID bits.
```

This also changes the behavior for the following case:

```
chmod u+s,g+s,o+x a
llvm-strip a
// a preserves set-user-ID and set-group-ID bits.
// This matches binutils<2.36 and probably >=2.37.  2.36 and 2.36.1 have some compatibility issues.
```

Differential Revision: https://reviews.llvm.org/D97253

[lldb] Support debugging utility functions

LLDB uses utility functions to run code in the inferior for its own
internal purposes, such as reading classes from the Objective-C runtime
for example. Because these expressions should be transparent to the
user, we ignore breakpoints and unwind the stack on errors, which
makes them hard to debug.

This patch adds a new setting target.debug-utility-expression that, when
enabled, changes these options to facilitate debugging. It enables
breakpoints, disables unwinding and writes out the utility function
source code to disk so it shows up in the source view.

Differential revision: https://reviews.llvm.org/D97249

[mlir][linalg] Support for using output values in TC definitions.

This will allow us to define select(pred, in, out) for TC ops, which is useful
for pooling ops.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97312

[mlir][linalg] Reuse the symbol if attribute uses are identical.

Depends On D97312

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97383

[mlir][docs] Small fix to local Pass Manager reproduction documentation

AMDGPU: Add even aligned VGPR/AGPR register classes

gfx90a operations require even aligned registers, but this was
previously achieved by reserving registers inside the full class.

Ideally this would be captured in the static instruction definitions
for the operands, and we would have different instructions per
subtarget. The hackiest part of this is we need to manually reassign
AGPR register classes after instruction selection (we get away without
this for VGPRs since those types are actually registered for legal
types).

AMDGPU: Remove special case in shouldCoalesce

Unaligned registers are now constrained with classes, rather than
specially reserving a subset of the whole class.

[InstCombine] add tests for fdiv+powi; NFC

[libcxx] [test] Quote the path to the python interpreter

This should allow running tests with the interpreter in some of the
default paths where Python for Windows might be installed.

Differential Revision: https://reviews.llvm.org/D97369

[amdgpu] Atomic should be source of divergence.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D97392

[tests] precommit tests for D97219

IR: Rename Metadata::ImplicitCode to SubclassData1, NFC

Metadata::ImplicitCode is a bit shaved off of Metadata::Storage,
currently only in use by the subclass DILocation. However, the bit isn't
reserved for that purpose. Rename it `SubclassData1` to make it clear
that it has nothing to do with Metadata itself (and other subclasses are
free to use it).

As a drive-by, remove an old TODO about exposing bits to subclasses
(looks like that has mostly been done).

No functionality change here.

Differential Revision: https://reviews.llvm.org/D96740