SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [AArch64][GlobalISel] Fix manual selection for v4s16 and v8s8 G_DUP (details)
  2. Remove a workaround for MSVC 2013, now that MSVC 2017 is the minimum. (details)
  3. [llvm-objcopy] If input=output, preserve umask bits, otherwise drop S_ISUID/S_ISGID bits (details)
  4. [lldb] Support debugging utility functions (details)
  5. [mlir][linalg] Support for using output values in TC definitions. (details)
  6. [mlir][linalg] Reuse the symbol if attribute uses are identical. (details)
  7. [mlir][docs] Small fix to local Pass Manager reproduction documentation (details)
  8. AMDGPU: Add even aligned VGPR/AGPR register classes (details)
  9. AMDGPU: Remove special case in shouldCoalesce (details)
  10. [InstCombine] add tests for fdiv+powi; NFC (details)
  11. [libcxx] [test] Quote the path to the python interpreter (details)
  12. [amdgpu] Atomic should be source of divergence. (details)
  13. [tests] precommit tests for D97219 (details)
  14. IR: Rename Metadata::ImplicitCode to SubclassData1, NFC (details)
Commit e339bba637b941c8e78057319b7654c4babf18cb by Jessica Paquette
[AArch64][GlobalISel] Fix manual selection for v4s16 and v8s8 G_DUP

The manual G_DUP selection code would produce DUPv16i8 for v8s8s and DUPv8i16
for v4s16.

This adds the missing cases to the manual selection code, and makes it return
false when there is an unexpected size.

Update select-dup.mir to reflect the change.

Differential Revision: https://reviews.llvm.org/D97240
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
Commit c2487bf7dfdda59b775b3d5a06684af243790125 by jyknight
Remove a workaround for MSVC 2013, now that MSVC 2017 is the minimum.

In MSVC 2013, 'alignas(integer-template-arg)' didn't compile; verified
on godbolt that this now works properly.
The file was modifiedllvm/include/llvm/Support/TrailingObjects.h
Commit 17b4e695ce0ef89eac4a37df2df49d4c0e700766 by i
[llvm-objcopy] If input=output, preserve umask bits, otherwise drop S_ISUID/S_ISGID bits

This makes the behavior similar to cp

```
chmod u+s,g+s,o+x a
sudo llvm-strip a -o b
// With this patch, b drops set-user-ID and set-group-ID bits.
// sudo cp a b => b does not have set-user-ID or set-group-ID bits.
```

This also changes the behavior for the following case:

```
chmod u+s,g+s,o+x a
llvm-strip a
// a preserves set-user-ID and set-group-ID bits.
// This matches binutils<2.36 and probably >=2.37.  2.36 and 2.36.1 have some compatibility issues.
```

Differential Revision: https://reviews.llvm.org/D97253
The file was modifiedllvm/tools/llvm-objcopy/llvm-objcopy.cpp
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/mirror-permissions-unix.test
Commit 38dfb235db19caa1aaa58c1c8153a7464b932087 by Jonas Devlieghere
[lldb] Support debugging utility functions

LLDB uses utility functions to run code in the inferior for its own
internal purposes, such as reading classes from the Objective-C runtime
for example. Because these expressions should be transparent to the
user, we ignore breakpoints and unwind the stack on errors, which
makes them hard to debug.

This patch adds a new setting target.debug-utility-expression that, when
enabled, changes these options to facilitate debugging. It enables
breakpoints, disables unwinding and writes out the utility function
source code to disk so it shows up in the source view.

Differential revision: https://reviews.llvm.org/D97249
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.h
The file was modifiedlldb/include/lldb/Expression/UtilityFunction.h
The file was modifiedlldb/source/Expression/UtilityFunction.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp
The file was modifiedlldb/source/Expression/FunctionCaller.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
The file was modifiedlldb/source/Target/Target.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.h
The file was modifiedlldb/source/Target/TargetProperties.td
The file was modifiedlldb/include/lldb/Target/Target.h
Commit 705068cb8c4d86c798c4134f0a332f4a45c7df04 by hanchung
[mlir][linalg] Support for using output values in TC definitions.

This will allow us to define select(pred, in, out) for TC ops, which is useful
for pooling ops.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97312
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOpsSpec.tc
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
Commit 21895a2beff7fcd92441c884de7c04f324996c79 by hanchung
[mlir][linalg] Reuse the symbol if attribute uses are identical.

Depends On D97312

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97383
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
Commit e79cd47e1620045562960ddfe17ab0c4f6e6628f by riddleriver
[mlir][docs] Small fix to local Pass Manager reproduction documentation
The file was modifiedmlir/docs/PassManagement.md
Commit 78b6d73a93fc6085d2a2fc84bdce1bbde740cf16 by Matthew.Arsenault
AMDGPU: Add even aligned VGPR/AGPR register classes

gfx90a operations require even aligned registers, but this was
previously achieved by reserving registers inside the full class.

Ideally this would be captured in the static instruction definitions
for the operands, and we would have different instructions per
subtarget. The hackiest part of this is we need to manually reassign
AGPR register classes after instruction selection (we get away without
this for VGPRs since those types are actually registered for legal
types).
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was removedllvm/test/CodeGen/AMDGPU/reserved-vgpr-tuples.mir
The file was modifiedllvm/lib/Target/AMDGPU/GCNSubtarget.h
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/dpp64_combine.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
Commit 589223e044dbea0554d2e8b54bf49e9cc278b643 by Matthew.Arsenault
AMDGPU: Remove special case in shouldCoalesce

Unaligned registers are now constrained with classes, rather than
specially reserving a subset of the whole class.
The file was modifiedllvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
Commit 3475159122b656ff098e2f44af32dc56f3beb610 by spatel
[InstCombine] add tests for fdiv+powi; NFC
The file was modifiedllvm/test/Transforms/InstCombine/fdiv.ll
Commit c218c80c730a14a1cbcebd588b18220a879702c6 by martin
[libcxx] [test] Quote the path to the python interpreter

This should allow running tests with the interpreter in some of the
default paths where Python for Windows might be installed.

Differential Revision: https://reviews.llvm.org/D97369
The file was modifiedlibcxx/test/CMakeLists.txt
Commit 0d4e12e3c110e5d73302a369f5e17d1fa67710e1 by michael.hliao
[amdgpu] Atomic should be source of divergence.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D97392
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
Commit 52745e4d907867bbb28fb8b0e8456915611a47a3 by listmail
[tests] precommit tests for D97219
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/post-increment-insertion.ll
Commit 1e1b92f76de79b934ead3be075aff101bd880392 by Duncan P. N. Exon Smith
IR: Rename Metadata::ImplicitCode to SubclassData1, NFC

Metadata::ImplicitCode is a bit shaved off of Metadata::Storage,
currently only in use by the subclass DILocation. However, the bit isn't
reserved for that purpose. Rename it `SubclassData1` to make it clear
that it has nothing to do with Metadata itself (and other subclasses are
free to use it).

As a drive-by, remove an old TODO about exposing bits to subclasses
(looks like that has mostly been done).

No functionality change here.

Differential Revision: https://reviews.llvm.org/D96740
The file was modifiedllvm/include/llvm/IR/DebugInfoMetadata.h
The file was modifiedllvm/include/llvm/IR/Metadata.h