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Summary

  1. [gn build] Port a8a43b63388 (details)
  2. [RISCV] Add tests for existing (rotr (bswap X), (i32 16))->grevi pattern for RV32. Extend same pattern to rotl and GREVIW. (details)
Commit 88974e829ec343ad9226982888807703a68acd98 by llvmgnsyncbot
[gn build] Port a8a43b63388
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn
Commit 6ee22ca6ceb71661e8dbc296b471ace0614c07e5 by craig.topper
[RISCV] Add tests for existing (rotr (bswap X), (i32 16))->grevi pattern for RV32. Extend same pattern to rotl and GREVIW.

Not sure why bswap was treated specially. This also applies to bitreverse
or generic grevi. We can improve this in future patches.
For now I just wanted to get the consistency and the test coverage
as I plan to make some other changes around bswap.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
The file was modifiedllvm/test/CodeGen/RISCV/rv64Zbp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbp.ll